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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16498
1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
DESCRIPTION
The PD16498 is a controller/driver which includes display RAM for full-dot LCDs that can provide a four-level gray scale display. This IC is able to drive full-dot LCDs that contain up to 128 x 128 dots.
FEATURES
* LCD controller/driver with on-chip display RAM * Full dot outputs: 128 segment outputs and 128 common outputs * Static icon outputs: 20 segment outputs and 2 common outputs (same signal is output) * Can operate using single power supply (logic system) in range from 1.7 to 3.6 V. * Selection of four levels of gray scales from among 33 possible levels (four-frame rate control + 8 pulse width modulation) * Serial data input and 8-bit parallel data input (i80 series interface and M68 series interface) * Dot display RAM: 128 x 128 x 2 bits * On-chip booster: Switchable from x2 to x9 modes * Selectable bias levels: 1/12 to 1/7 bias (normal display), 1/6 or 1/5 bias (partial display) * Duty settings: 1/128 to 1/1 duty * On-chip voltage divider resistor * On-chip oscillator
ORDERING INFORMATION
Part Number Package Chip Wafer
PD16498P PD16498W
Remark Purchasing the chip/wafer entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15730EJ2V0DS00 (2nd Edition) Date Published June 2002 NS CP(K)
2001
PD16498
TABLE OF CONTENTS
1. BLOCK1. BLOCK DIAGRAM ................................................................................................................... 5 2. PIN CONFIGURATION (PAD LAYOUT) ................................................................................................... 6 3. PIN FUNCTIONS ...................................................................................................................................... 10
3.1 Power Supply System Pins ............................................................................................................................ 10 3.2 Logic System Pins .......................................................................................................................................... 11 3.3 Driver-Related Pins ......................................................................................................................................... 13 3.4 Test Pins ......................................................................................................................................................... 14
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS .................................... 15 5. DESCRIPTION OF FUNCTIONS ............................................................................................................. 16
5.1 CPU Interface ....................................................................................................................................... 16 5.1.1 Selection of interface type ............................................................................................................ 16 5.1.2 Parallel interface ........................................................................................................................... 16 5.1.3 Serial interface ............................................................................................................................ 18 5.1.4 Chip select ................................................................................................................................... 18 5.1.5 Display data RAM and on-chip register access ................................................................................ 18 5.2 Display Data RAM ................................................................................................................................ 21 5.2.1 Display data RAM .................................................................................................................................... 21 5.2.2 X address circuit ..................................................................................................................................... 21 5.2.3 Column address circuit ............................................................................................................................ 23 5.2.4 Y address circuit ...................................................................................................................................... 23 5.2.5 Common scan circuit ............................................................................................................................... 23 5.2.6 Display start line set ................................................................................................................................. 23 5.2.7 Display data latch circuit .......................................................................................................................... 23 5.3 Blink/Reverse Display Circuit ......................................................................................................................... 24 5.4 Oscillator .......................................................................................................................................................... 26 5.5 Display Timing Generator ............................................................................................................................... 30 5.6 Power Supply Circuit ....................................................................................................................................... 31 5.6.1 Booster .................................................................................................................................................... 31 5.6.2 Voltage regulator ..................................................................................................................................... 33 5.6.3 Use of op amp for level power supply control .......................................................................................... 36 5.6.4 Application examples of power supply circuits ......................................................................................... 37 5.7 LCD Display Drivers ........................................................................................................................................ 40 5.7.1 Full-dot pulse width modulation ............................................................................................................... 40 5.7.2 Full-dot frame rate control ........................................................................................................................ 45 5.7.3 Line shift driver ........................................................................................................................................ 46 5.7.4 Display size settings ................................................................................................................................ 48 5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position ......................................... 48
2
Data Sheet S15730EJ2V0DS
PD16498
5.8 Display Modes .................................................................................................................................................. 50 5.8.1 Partial display mode ................................................................................................................................ 50 5.8.2 Monochrome (black/white) display ........................................................................................................... 52 5.8.3 Icon display .............................................................................................................................................. 54 5.9 Reset ................................................................................................................................................................. 56
6. COMMAND REGISTERS .......................................................................................................................... 57
6.1 Control Register 1 (R0) .................................................................................................................................... 58 6.2 Control Register 2 (R1) .................................................................................................................................... 59 6.3 Reset Command (R2) ....................................................................................................................................... 60 6.4 X Address Register (R3) .................................................................................................................................. 60 6.5 Y Address Register (R4) .................................................................................................................................. 60 6.6 Duty Setting Register (R5) .............................................................................................................................. 61 6.7 AC Driver Inversion Cycle Register (R6) ........................................................................................................ 61 6.8 AC Driver Inversion Position Shift Register (R7) .......................................................................................... 62 6.9 Partial AC Driver Inversion Cycle Register (R8) ............................................................................................ 62 6.10 Partial AC Driver Inversion Position Shift Register (R9) ............................................................................ 63 6.11 Partial Display Mode Setting Register (R10) ................................................................................................ 63 6.12 Display Memory Access Register (R11)........................................................................................................ 64 6.13 Display Start Line Setting Register (R12) ..................................................................................................... 64 6.14 Blink X Address Register (R13) .................................................................................................................... 64 6.15 Blink Start Line Address Register (R14) ...................................................................................................... 65 6.16 Blink End Line Address Register (R15) ....................................................................................................... 65 6.17 Blink Data Memory Access Register (R16) .................................................................................................. 65 6.18 Inverted X Address Register (R17) ............................................................................................................... 66 6.19 Inversion Start Line Address Register (R18) ................................................................................................ 66 6.20 Inversion End Line Address Register (R19) ................................................................................................ 66 6.21 Inverted Data Memory (R20) .......................................................................................................................... 67 6.22 Partial Start Line Address Register (R21) .................................................................................................... 67 6.23 Gray Scale Data Registers 1 to 4 (R23 to R26) ............................................................................................ 68 6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30) ................................................................................ 68 6.25 Power System Control Register 1 (R32) ...................................................................................................... 69 6.26 Power System Control Register 2 (R33) ...................................................................................................... 70 6.27 Power System Control Register 3 (R34) ...................................................................................................... 71 6.28 Electronic Volume Register (R35) ................................................................................................................ 72 6.29 Partial Electronic Volume Register (R36) .................................................................................................... 72 6.30 Boost Adjustment Register (R37) ................................................................................................................. 72 6.31 Static Icon Address Register (R40) ............................................................................................................. 73 6.32 Static Icon Data Register (R41) ..................................................................................................................... 73 6.33 Static Icon Contrast Register (R42) .............................................................................................................. 73 6.34 RAM Test Mode Setting Register (R44) ........................................................................................................ 74 6.35 Signature Read Register (R45) ..................................................................................................................... 74
7. LIST OF PD16498 REGISTERS ............................................................................................................ 75
Data Sheet S15730EJ2V0DS
3
PD16498
8. POWER SUPPLY SEQUENCE ................................................................................................................ 76
8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON Display ON) ................ 76 8.2 Power OFF Sequence (When Using On-Chip Power Supply) ...................................................................... 77 8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON Display ON) ................. 77 8.4 Power Supply OFF Sequence (When Using External Driver Power Supply) .............................................. 78 8.5 VOUT, VLCD Voltage Sequence (Power ON Power OFF) .............................................................................. 79
9. USE OF RAM TEST MODE ..................................................................................................................... 80 10. USE OF STANDBY/HALT MODE ......................................................................................................... 81 11. ELECTRICAL SPECIFICATIONS .......................................................................................................... 82 12. CPU INTERFACE (REFERENCE EXAMPLE) ...................................................................................... 91
4
Data Sheet S15730EJ2V0DS
PD16498
1. BLOCK DIAGRAM
SEG1 SEG128 COM1 COM128 PCOM1 PCOM2
Data register
Segment driver
Common driver
Pictograph common driver
/RES /CS1 CS2 C86 PSX RDS /RD(E) /WR(R,/W) P7(SI) P6(SCL) P5 to P0 RS IRS TM/S TFR TFRSYNC TDOF TSISYNC SIGIN1 SIGIN2 TSTIFS TSTRTST TSTVIHL TESTOUT OSCIN1 OSCIN2 OSCOUT TOSCSYNC CLS + C1 , C1
Segment G/S and blink control
Pictograph segment driver
PSEG1
PSEG20
Display data latch Common timing generator Pictograph common timing generator
I/O buffer
Display data RAM (128 x 128 x 2 bits)
Icon data RAM (20 x 2 bits)
Address decoder
Command decoder
Register
Segment G/S and blink timer
Oscillator circuit D/A converter
Timing generator
DC/DC converter + C9 , C9 C1A
Op amp
LCD voltage generator
VOUT
VRS
IRS
VR
AMPOUTP AMPOUT
VLCD
VLC1
VLC2
VLC3
VLC4
VDD1 VDD2 VSS
Remark /xxx indicates active low signals.
Data Sheet S15730EJ2V0DS
5
PD16498
2. PIN CONFIGURATION (PAD LAYOUT)
Chip size Chip 3.0 x 11.4 mm2 485 m TYP.
A1
489
451
A4
1
450
Y X
211
251 A3
A2
212
6
Data Sheet S15730EJ2V0DS
PD16498
*PD16498 Pad Layout (1/3)
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pin Name DUMMY DUMMY PSEG1 PSEG1 DUMMY PSEG2 PSEG2 PSEG3 PSEG3 DUMMY PSEG4 PSEG4 PSEG5 PSEG5 DUMMY PSEG6 PSEG6 PSEG7 PSEG7 DUMMY PSEG8 PSEG8 PSEG9 PSEG9 DUMMY PSEG10 PSEG10 VSS VRS VRS AMPOUTP AMPOUTP AMPOUT AMPOUT VR VR VLC4 VLC4 VLC3 VLC3 VLC2 VLC2 VLC1 VLC1 VLCD VLCD VSS VOUT VOUT VSS C9C9C9+ C9+ C8C8C8+ C8+ C7C7C7+ C7+ C6C6C6+ C6+ C5C5C5+ C5+ Pad Type B A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Coordinate X[ m] Y[ m] -1383.500 5341.000 -1383.500 5250.000 -1383.500 5150.000 -1383.500 5100.000 -1383.500 5050.000 -1383.500 5000.000 -1383.500 4950.000 -1383.500 4900.000 -1383.500 4850.000 -1383.500 4800.000 -1383.500 4750.000 -1383.500 4700.000 -1383.500 4650.000 -1383.500 4600.000 -1383.500 4550.000 -1383.500 4500.000 -1383.500 4450.000 -1383.500 4400.000 -1383.500 4350.000 -1383.500 4300.000 -1383.500 4250.000 -1383.500 4200.000 -1383.500 4150.000 -1383.500 4100.000 -1383.500 4050.000 -1383.500 4000.000 -1383.500 3950.000 -1383.500 3900.000 -1383.500 3850.000 -1383.500 3800.000 -1383.500 3750.000 -1383.500 3700.000 -1383.500 3650.000 -1383.500 3600.000 -1383.500 3550.000 -1383.500 3500.000 -1383.500 3450.000 -1383.500 3400.000 -1383.500 3350.000 -1383.500 3300.000 -1383.500 3250.000 -1383.500 3200.000 -1383.500 3150.000 -1383.500 3100.000 -1383.500 3050.000 -1383.500 3000.000 -1383.500 2950.000 -1383.500 2900.000 -1383.500 2850.000 -1383.500 2800.000 -1383.500 2750.000 -1383.500 2700.000 -1383.500 2650.000 -1383.500 2600.000 -1383.500 2550.000 -1383.500 2500.000 -1383.500 2450.000 -1383.500 2400.000 -1383.500 2350.000 -1383.500 2300.000 -1383.500 2250.000 -1383.500 2200.000 -1383.500 2150.000 -1383.500 2100.000 -1383.500 2050.000 -1383.500 2000.000 -1383.500 1950.000 -1383.500 1900.000 -1383.500 1850.000 -1383.500 1800.000 Pad No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Pin Name C4C4C4+ C4+ C3C3C3+ C3+ C2C2C2+ C2+ C1C1C1+ C1+ C1A C1A VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VSS VSS VSS CLS CLS VDD1 TM/S TM/S VSS C86 C86 /PSX /PSX VDD1 IRS IRS VSS /CS1 /CS1 CS2 CS2 VDD1 /RES /RES RS RS VSS WR (R,/W) WR (R,/W) /RD (E) /RD (E) VDD1 RDS RDS VSS P7 (SI) P7 (SI) P6 (SCL) P6 (SCL) DUMMY P5 P5 P4 P4 DUMMY P3 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Coordinate X[ m] Y[ m] -1383.500 1750.000 -1383.500 1700.000 -1383.500 1650.000 -1383.500 1600.000 -1383.500 1550.000 -1383.500 1500.000 -1383.500 1450.000 -1383.500 1400.000 -1383.500 1350.000 -1383.500 1300.000 -1383.500 1250.000 -1383.500 1200.000 -1383.500 1150.000 -1383.500 1100.000 -1383.500 1050.000 -1383.500 1000.000 -1383.500 950.000 -1383.500 900.000 -1383.500 850.000 -1383.500 800.000 -1383.500 750.000 -1383.500 700.000 -1383.500 650.000 -1383.500 600.000 -1383.500 550.000 -1383.500 500.000 -1383.500 450.000 -1383.500 400.000 -1383.500 350.000 -1383.500 300.000 -1383.500 250.000 -1383.500 200.000 -1383.500 150.000 -1383.500 100.000 -1383.500 50.000 -1383.500 0.000 -1383.500 -50.000 -1383.500 -100.000 -1383.500 -150.000 -1383.500 -200.000 -1383.500 -250.000 -1383.500 -300.000 -1383.500 -350.000 -1383.500 -400.000 -1383.500 -450.000 -1383.500 -500.000 -1383.500 -550.000 -1383.500 -600.000 -1383.500 -650.000 -1383.500 -700.000 -1383.500 -750.000 -1383.500 -800.000 -1383.500 -850.000 -1383.500 -900.000 -1383.500 -950.000 -1383.500 -1000.000 -1383.500 -1050.000 -1383.500 -1100.000 -1383.500 -1150.000 -1383.500 -1200.000 -1383.500 -1250.000 -1383.500 -1300.000 -1383.500 -1350.000 -1383.500 -1400.000 -1383.500 -1450.000 -1383.500 -1500.000 -1383.500 -1550.000 -1383.500 -1600.000 -1383.500 -1650.000 -1383.500 -1700.000 Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Pad Type P3 A P2 A P2 A DUMMY A P1 A P1 A P0 A P0 A DUMMY A TFRSYNC A TFRSYNC A TFR A TFR A DUMMY A TDOF A TDOF A OSCIN1 A OSCIN1 A OSCIN2 A OSCIN2 A OSCOUT A OSCOUT A DUMMY A TOSCSYNC A TOSCSYNC A TSISYNC A TSISYNC A VSS A SIGIN1 A SIGIN1 A VDD1 A SIGIN2 A SIGIN2 A VSS A TESTOUT A TESTOUT A TSTIFS A TSTIFS A TSTRTST A TSTRTST A TSTVIHL A TSTVIHL A VSS A PSEG11 A PSEG11 A DUMMY A PSEG12 A PSEG12 A PSEG13 A PSEG13 A DUMMY A PSEG14 A PSEG14 A PSEG15 A PSEG15 A DUMMY A PSEG16 A PSEG16 A PSEG17 A PSEG17 A DUMMY A PSEG18 A PSEG18 A PSEG19 A PSEG19 A DUMMY A PSEG20 A PSEG20 A DUMMY A DUMMY A Pin Name Pad Coordinate X[ m] Y[ m] -1383.500 -1750.000 -1383.500 -1800.000 -1383.500 -1850.000 -1383.500 -1900.000 -1383.500 -1950.000 -1383.500 -2000.000 -1383.500 -2050.000 -1383.500 -2100.000 -1383.500 -2150.000 -1383.500 -2200.000 -1383.500 -2250.000 -1383.500 -2300.000 -1383.500 -2350.000 -1383.500 -2400.000 -1383.500 -2450.000 -1383.500 -2500.000 -1383.500 -2550.000 -1383.500 -2600.000 -1383.500 -2650.000 -1383.500 -2700.000 -1383.500 -2750.000 -1383.500 -2800.000 -1383.500 -2850.000 -1383.500 -2900.000 -1383.500 -2950.000 -1383.500 -3000.000 -1383.500 -3050.000 -1383.500 -3100.000 -1383.500 -3150.000 -1383.500 -3200.000 -1383.500 -3250.000 -1383.500 -3300.000 -1383.500 -3350.000 -1383.500 -3400.000 -1383.500 -3450.000 -1383.500 -3500.000 -1383.500 -3550.000 -1383.500 -3600.000 -1383.500 -3650.000 -1383.500 -3700.000 -1383.500 -3750.000 -1383.500 -3800.000 -1383.500 -3850.000 -1383.500 -3900.000 -1383.500 -3950.000 -1383.500 -4000.000 -1383.500 -4050.000 -1383.500 -4100.000 -1383.500 -4150.000 -1383.500 -4200.000 -1383.500 -4250.000 -1383.500 -4300.000 -1383.500 -4350.000 -1383.500 -4400.000 -1383.500 -4450.000 -1383.500 -4500.000 -1383.500 -4550.000 -1383.500 -4600.000 -1383.500 -4650.000 -1383.500 -4700.000 -1383.500 -4750.000 -1383.500 -4800.000 -1383.500 -4850.000 -1383.500 -4900.000 -1383.500 -4950.000 -1383.500 -5000.000 -1383.500 -5050.000 -1383.500 -5100.000 -1383.500 -5200.000 -1383.500 -5250.000
Data Sheet S15730EJ2V0DS
7
PD16498
*PD16498 Pad Layout (2/3)
Pad No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Pin Name DUMMY DUMMY DUMMY PCOM1 PCOM1 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 COM64 DUMMY DUMMY DUMMY DUMMY DUMMY COM66 COM68 COM70 COM72 COM74 COM76 COM78 COM80 COM82 COM84 COM86 COM88 COM90 COM92 COM94 COM96 COM98 COM100 COM102 COM104 COM106 COM108 COM110 COM112 COM114 COM116 COM118 COM120 Pad Type B B A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Coordinate Y[ m] X[ m] -1383.500 -1201.000 -1110.000 -1010.000 -960.000 -910.000 -860.000 -810.000 -760.000 -710.000 -660.000 -610.000 -560.000 -510.000 -460.000 -410.000 -360.000 -310.000 -260.000 -210.000 -160.000 -110.000 -60.000 -10.000 40.000 90.000 140.000 190.000 240.000 290.000 340.000 390.000 440.000 490.000 540.000 590.000 640.000 781.000 911.000 1041.000 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 -5341.000 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5482.760 -5226.000 -5096.000 -4875.000 -4825.000 -4775.000 -4725.000 -4675.000 -4625.000 -4575.000 -4525.000 -4475.000 -4425.000 -4375.000 -4325.000 -4275.000 -4225.000 -4175.000 -4125.000 -4075.000 -4025.000 -3975.000 -3925.000 -3875.000 -3825.000 -3775.000 -3725.000 -3675.000 -3625.000 -3575.000 -3525.000 Pad No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Pin Name COM122 COM124 COM126 COM128 DUMMY DUMMY SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Coordinate X[ m] Y[ m] 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 -3475.000 -3425.000 -3375.000 -3325.000 -3275.000 -3225.000 -3175.000 -3125.000 -3075.000 -3025.000 -2975.000 -2925.000 -2875.000 -2825.000 -2775.000 -2725.000 -2675.000 -2625.000 -2575.000 -2525.000 -2475.000 -2425.000 -2375.000 -2325.000 -2275.000 -2225.000 -2175.000 -2125.000 -2075.000 -2025.000 -1975.000 -1925.000 -1875.000 -1825.000 -1775.000 -1725.000 -1675.000 -1625.000 -1575.000 -1525.000 -1475.000 -1425.000 -1375.000 -1325.000 -1275.000 -1225.000 -1175.000 -1125.000 -1075.000 -1025.000 -975.000 -925.000 -875.000 -825.000 -775.000 -725.000 -675.000 -625.000 -575.000 -525.000 -475.000 -425.000 -375.000 -325.000 -275.000 -225.000 -175.000 -125.000 -75.000 -25.000 Pad No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 Pin Name SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY DUMMY COM127 COM125 COM123 COM121 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Coordinate X[ m] Y[ m] 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 25.000 75.000 125.000 175.000 225.000 275.000 325.000 375.000 425.000 475.000 525.000 575.000 625.000 675.000 725.000 775.000 825.000 875.000 925.000 975.000 1025.000 1075.000 1125.000 1175.000 1225.000 1275.000 1325.000 1375.000 1425.000 1475.000 1525.000 1575.000 1625.000 1675.000 1725.000 1775.000 1825.000 1875.000 1925.000 1975.000 2025.000 2075.000 2125.000 2175.000 2225.000 2275.000 2325.000 2375.000 2425.000 2475.000 2525.000 2575.000 2625.000 2675.000 2725.000 2775.000 2825.000 2875.000 2925.000 2975.000 3025.000 3075.000 3125.000 3175.000 3225.000 3275.000 3325.000 3375.000 3425.000 3475.000
8
Data Sheet S15730EJ2V0DS
PD16498
*PD16498 Pad Layout (3/3)
Pad No. 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 Pin Name COM119 COM117 COM115 COM113 COM111 COM109 COM107 COM105 COM103 COM101 COM99 COM97 COM95 COM93 COM91 COM89 COM87 COM85 COM83 COM81 COM79 COM77 COM75 COM73 COM71 COM69 COM67 COM65 DUMMY DUMMY DUMMY DUMMY DUMMY COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 PCOM2 PCOM2 DUMMY DUMMY Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B Pad Coordinate X[ m] Y[ m] 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1282.760 1041.000 911.000 781.000 665.000 615.000 565.000 515.000 465.000 415.000 365.000 315.000 265.000 215.000 165.000 115.000 65.000 15.000 -35.000 -85.000 -135.000 -185.000 -235.000 -285.000 -335.000 -385.000 -435.000 -485.000 -535.000 -585.000 -635.000 -685.000 -735.000 -785.000 -835.000 -885.000 -935.000 -985.000 -1085.000 -1176.000 3525.000 3575.000 3625.000 3675.000 3725.000 3775.000 3825.000 3875.000 3925.000 3975.000 4025.000 4075.000 4125.000 4175.000 4225.000 4275.000 4325.000 4375.000 4425.000 4475.000 4525.000 4575.000 4625.000 4675.000 4725.000 4775.000 4825.000 4875.000 5081.000 5211.000 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 5482.760 A1 A2 A3 A4
Pad type A: Pad size (Al) : 43 x 73 m 2 TYP. Bump size : 37 x 65 m 2 TYP. Bump height : 17 m TYP. Pad type B: Pad size (Al) : 118 x 73 m 2 TYP. Bump size : 110 x 65 m 2 TYP. Bump height : 17 m TYP.
Alingment Mark
Mark Center Coordinate Y [ m] X [ m] -1103.92 -1130.20 1274.78 1274.78 5193.00 -5217.10 -5474.78 5474.78
Alingment Mark Form Coordinate (Unit : m)
100
40
40 100
Data Sheet S15730EJ2V0DS
9
PD16498
3. PIN FUNCTIONS
3.1
VDD1 VDD2 VSS
Power Supply System Pins
Symbol pin Boost circuit power supply pin Logic and driver ground pin 28, 47, 50, 95 to 97, 103, 111, 121, 129, 168, 174, 183, 48, 49 - Power supply pin for driver. Output pin for on-chip booster. Connect a 1 F boost capacitor between this pin and the GND pin. If not using the on-chip booster, a direct driver power supply can be input. - Ground pin for logic and driver circuits Name Logic power supply Pad No. 92 to 94, 100, 108, 116, 126, 171 89 to 91, - Power supply pin for booster I/O - Description Power supply pin for logic circuit
VOUT
Driver power supply pin
VLCD, VLC1 to VLC4 C1 , C1
+ -
Reference power supply pins for driver Boost capacitor connection pins (1)
46, 45, 44 to 37 86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51,
-
These are reference power supply pins for the LCD driver. Connect a capacitor between these pins and the GND pin if an internal bias has been selected.
-
These are capacitor connection pins for the booster. When using the on-chip booster, connect a 1 F capacitor between positive (+) and negative (-) pins.
C2+, C2- C3+, C3- C4+, C4- C5 , C5
+ -
C6+, C6- C7+, C7- C8+, C8- C9 , C9 C1A
+ -
Boost capacitor connection pin (2)
87, 88
-
This is a capacitor connection pin for boost adjustment. When using the on-chip booster, connect a 1 F capacitor between this pin and the GND pin.
10
Data Sheet S15730EJ2V0DS
PD16498
3.2 Logic System Pins
(1/2)
Symbol PSX Name Data transfer selection Pad No. 106, 107 I/O Input data input. PSX = H: Parallel data input PSX = L: Serial data input /CS1, CS2 /RD (E) Read (enable) Chip select 112, 113, 114, 115 124, 125 Input Input These pins are used for chip select signals. When /CS1 = L (CS2 = H), the chip is active and can perform data input/output operations including command and data I/O. When i80 series parallel data transfer (/RD) has been selected, the signal at this pin is used to enable read operations. Data is output to the data bus only when this pin is L. When M68 series parallel data transfer (E) has been selected, the signal at this pin is used to enable write operations. Data is written at the falling edge of this signal. /WR (R,/W) Write (read/write) 122, 123 Input When i80 series parallel data transfer (/WR) has been selected, the signal at this pin is used to enable write operations. Data is written at the rising edge of this signal. When 68 series parallel data transfer (R,/W) has been selected, this pin is used to determine the direction of data transfer. L: Write H: Read C86 Interface selection 104, 105 Input This pin is used to switch between interface modes (i80 series CPU or M68 series CPU). L: Selects i80 series CPU mode H: Selects M68 series CPU mode RDS Data pin selection 127,128 Input This pin determines the direction of a data as follows. Fixed to low level at the time serial data input (PSX = L). RDS Low High P0 to P5, P6 (SCL) P7 (SI) Data bus (serial clock) (serial input) 131, 130 148 to 145, 143 to 140, 138 to 135, 133, 132, I/O P7 D7 D0 P6 D6 D1 P5 D5 D2 P4 D4 D3 P3 D3 D4 P2 D2 D5 P1 D1 D6 P0 D0 D7 Description This pin is used to select between parallel data input and serial
These pins comprise an 8-bit bidirectional data bus that connects to an 8-bit or 16-bit standard CPU bus. When the serial interface has been selected (PSX = L), P6 functions as a serial clock input pin (SCL) and P7 functions as a serial data input pin (SI). In either case, pins P0 to P5 are in high impedance mode. When the chip is not selected, P0 to P7 are in high impedance mode.
RS
Index register/data, command selection
119, 120
Input
Usually, this pin is connected to the LSB of the standard CPU address bus and is used to distinguish between data from index registers and data/commands. RS = H: Indicates that data from D0 to D7 is data/command RS = L : Indicates that data from D0 to D7 is index register contents
/RES
Reset
117, 118
Input
When /RES is low, an internal reset is performed. The reset operation is executed at the /RES signal level.
Data Sheet S15730EJ2V0DS
11
PD16498
(2/2)
Symbol CLS Name Select clock division Pad No. 98, 99 I/O Input Description This pin is used to select whether or not to use the divider within the display clock oscillator. CLS = H: Use divider CLS = L: Do not use divider When using an external clock, the CLS = L setting is input via the OSCIN1 and OSCIN2 pins as normal and partial clocks respectively. When CLS = H, clock input is via the OSCIN1 pin only. IRS VLCD regulation 109, 110 Input This pin is used to select the resistor that is used for VLCD voltage regulation. IRS = H: Uses internal resistor IRS = L: Does not use internal resistor. The VLCD voltage level is regulated using the external voltage division resistor that is connected to the VR pin. This pin is valid only in master operation mode. In slave operation mode, this pin is fixed high or low level. SIGIN1, SIGIN2 OSCIN1 OSCIN2 OSCOUT Signature setting pins Oscillation signal pins 159, 160 161, 162 Input Output 169, 170, 172, 173 157, 158 Input Input These pins can be used to set a unique signature for the IC. The signal set via these pins can subsequently be read from the signature read register (R45). A resistor can be inserted between OSCIN1- OSCOUT, and OSCIN2OSCOUT. When using an external oscillator, a clock signal is input via the OSCIN pins according to the CLS pin's status and the OSCOUT pin is left unconnected. The wiring between OSCIN1-OSCOUT and OSCIN2-OSCOUT must be as short as possible, and use after proper evaluation.
12
Data Sheet S15730EJ2V0DS
PD16498
3.3 Driver-Related Pins
Symbol SEG1 to SEG128 COM1 to COM128 PSEG1 to PSEG20 Static segment Common 216 to 247, 253 to 284, Output 417 to 448, 454 to 485 3, 4, 6 to 9, 11 to 14, 16 to 19, 21 to 24, 26, 27, 184, 185, 187 to 190, 192 to 195, 197 to 200, 202 to 205, 207, 208 PCOM1, PCOM2 VRS Op amp input pin for regulating the driving voltage of the LCD Static common 214, 215, 486, 487 29, 30 Input Output Common output pins for static icon (Same driver waveform is output from two pins.) VRS is an op amp input pin for regulating the driving voltage of the LCD. This is a reference voltage input for the LCD voltage regulation amplifier. When using the internal drive circuit (i.e., when OP1 = 1), we recommend inserting a 0.1 to 1 F capacitor between this pin and GND. VR Input pin for the op amp's feedback connection 35, 36 Input VR is an input for the op amp's feedback connection. Insert this pin between GND and AMPOUT when using the feedback resistor for this input. This pin is valid only when not using an internal resistor for VLCD voltage regulation (i.e., when IRS = L). This pin cannot be used when using the internal resistor for VLCD voltage regulation (i.e., when IRS = H). AMPOUT Op amp output 33, 34 Output These are op amp output pins for regulating the driving voltage of the LCD. When not using an internal resistor for VLCD voltage regulation (i.e., when IRS = L), these outputs are connected to the AMPOUTP 31, 32 LCD drive voltage regulation resistor (see 5.6.2 Voltage regulator). We recommend inserting a 0.01 to 0.1 F capacitor between these pins in order to stabilize the internal op amp's output. DUMMY Dummy pin 1, 2, 5, 10, 15, 20, 25, 134, 139, 144, 149, 154, 163, 186, 191, 196, 201, 206, 209 to 213, 248 to 252, 415, 416, 449 to 453, 488, 489 - Dummy pin. These pins are not connected inside IC. Usually, leave these pins open. Output Segment output pins for static icon Common output pins Name Segment Pad No. 414 to 287 I/O Output Segment output pins Description
Data Sheet S15730EJ2V0DS
13
PD16498
3.4
TFR TFRSYNC TDOF TSISYNC TOSCSYNC TESTOUT TM/S TSTIFS TSTRTST TSTVIHL Test input Test input
Test Pins
Symbol Name Test output Pad No. 152, 153 150, 151 155, 156 166, 167 164, 165 175, 176 101, 102 177, 178 179, 180 181, 182 Input Input These pins are used to set a test mode for the IC. Normally, connect these pins to VDD1. These pins are used to set a test mode for the IC. Normally, connect these pins to VSS. I/O Output Usually, leave them open. Description These pins are used when the IC is in test mode.
14
Data Sheet S15730EJ2V0DS
PD16498
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit type of each pin and recommended connection of unused pins are described below.
Pin Name PSX /CS1 CS2 /RD(E) /WR(R,/W) C86 RDS P0 to P5 P6(SCL) P7(SI) RS /RES CLS IRS SIGIN1 SIGIN2 OSCIN1 OSCIN2 OSCOUT TFR TFRSYNC TDOF TSISYNC TM/S TOSCSYNC TSTIFS TSTRTST TSTVIHL TESTOUT CMOS CMOS CMOS CMOS Schmitt trigger - Schmitt trigger Schmitt trigger Schmitt trigger Input Type Schmitt trigger Filter Filter Filter Filter Schmitt trigger Schmitt trigger Filter Filter Filter Filter Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger - Input/output Input Input Input Input Input Input Input Input/output Input/output Input/output Input Input Input Input Input Input Input Input Output Output Output Output Output Input Output Input Input Input Output Register setting pin. Connect to VDD1. Mode setting pin Mode setting pin. Connect to VDD1 or VSS. Connect to VDD1 or VSS. - Connect to VDD1 or VSS (CLS = H) Leave open (when using external clock) Leave open Leave open Leave open Leave open Connect to VDD1 Leave open Connect to VSS (during normal use) Connect to VSS (during normal use) Connect to VSS (during normal use) Leave open Recommended Connection of Unused Pins Mode setting pin. Connect to VSS. Connect to VDD1. Connect to VDD1 (i80 series interface), connect to VDD1 or VSS (serial interface). Connect to VDD1 or VSS (serial interface). Mode setting pin. Mode setting pin. Leave open - - - Note 1 Note 1 - - - Note 2 - Note 1 Note 1 - - - - - - - - - - - - - - - Notes Note 1 - - -
Notes 1. Connect to either VDD1 or VSS, depending on the mode setting. 2. Input either VDD1 or VSS output from CPU, depending on the mode setting.
Data Sheet S15730EJ2V0DS
15
PD16498
5. DESCRIPTION OF FUNCTIONS
5.1 CPU Interface
5.1.1 Selection of interface type The PD16498 chip transfers data using an 8-bit bidirectional data bus (P7 to P0) or a serial data input (SI). Setting the polarity of the PSX pin as either H (high) or L (low) selects between 8-bit parallel or serial data input, as shown in the following table.
PSX H: Parallel input L: Serial input CS CS CS RS RS RS /RD /RD
Note1
/WR /WR
Note1
C86 C86
Note1
RDS L H LNote2
P7 D7 D7 SI
P6 D6 D6 SCL
P5 D5 D5
P4 D4 D4
P3 D3 D3
P2 D2 D2
P1 D1 D1
P0 D0 D0
Hi-ZNote3
Notes 1. Fixed as either High or Low. 2. Fix the RDS pin to Low level when the serial interface has been selected (PSX = L). 3. Hi-Z: High impedance
5.1.2 Parallel interface When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection to an i80 series or M68 series CPU (see table below).
C86 H: M68 series CPU L: i80 series CPU /CS1 /CS1 /CS1 CS2 CS2 CS2 RS RS RS /RD E /RD /WR R,/W /WR P7 to P0 D7 to D0 D7 to D0
The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the following table.
Common RS 1 1 0 0 M68 R,/W 1 0 1 0 /RD 0 1 0 1 i80 /WR 1 0 1 0 Reads display data and registers Writes display data and registers Prohibited Writes to index register Function
16
Data Sheet S15730EJ2V0DS
PD16498
(1) i80 series parallel interface When i80 series parallel data transfer has been selected, data is written to the PD16498 at the rising edge of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 5-1. i80 Series Interface Data Bus Status
/CS1 (CS2=H)
/WR
/RD
Hi-Z DBn Data write Valid data Data Read
Hi-Z
(2) M68 series parallel interface When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H, outputs valid data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the R,/W signal (R,/W = L) Figure 5-2. M68 Series Interface Data Bus Status
/CS1 (CS2=H)
R,/W
E
Hi-Z DBn Invalid data Valid data
Hi-Z
Data Sheet S15730EJ2V0DS
17
PD16498
5.1.3 Serial interface When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to parallel data for processing. RS input is used to judge serial input data as display data or command data: when RS = H the data is display/command data and when RS = L the data is index data. When the chip enters active mode, RS input is read at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal chart is shown below. Figure 5-3. Serial Interface Signal Chart
CS2="H" /CS1 SI SCL 1 RS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings. 2. The data read function is disabled during serial interface mode. 3. When using SCL wiring, take care concerning the possible effects of terminating reflection and noise from external sources. We recommend checking operation with the actual device.
5.1.4 Chip select The PD16498 has two chip select pins (/CS1 and CS2). The CPU parallel interface or serial interface can be used only when /CS1 = L and CS2 = H. When chip select is inactive, P0 to P7 are set to high impedance (invalid) and input of RS, /RD, or /WR is not active. If serial interface mode has been set, the shift register and counter are both reset.
5.1.5 Display data RAM and on-chip register access Because only the required cycle time (tcyc) is satisfied when accessing the PD16498 from the CPU, high-speed data transfer is possible. There is no need to consider any wait time. No dummy data is needed when writing data. Even when data is read, there is no need for dummy data except in the display memory access register (R11). In other words, dummy data is required only when reading data from the display memory access register (R11). Figure 5-4 illustrates this relationship.
18
Data Sheet S15730EJ2V0DS
PD16498
Figure 5-4. Write and Read (1/2) Write

/WR
DATA
N
N+1
N+2
N+3

BUS holder
Latch
N
N+1
N+2
N+3
Write signal
Read (display memory access register (R11))

/WR
/RD
DATA
N
N
n
n+1

Address preset
Read signal Column address
Preset N
Increment N + 1
N+2
BUS holder
N
n
n+1
n+2
Address set #n
Dummy read
Data read #n
Data read #n + 1
Data Sheet S15730EJ2V0DS
19
PD16498
Figure 5-4. Write and Read (2/2) Read (other than display memory access register)

/WR
/RD
DATA
IRn
IRn data
IRn+1
IRn + 1 Data
IR address set #n
IRn register data read
IR address set #n + 1
IRn + 1 register data read
20
Data Sheet S15730EJ2V0DS
PD16498
5.2 Display Data RAM
5.2.1 Display data RAM This is the RAM that is used to store the display's dot data. The RAM configuration is 256 bits (32 x 8 bits) x 128 bits. Any specified bit can be accessed by selecting the corresponding X address and Y address. The display data D0 to D7 sent from the CPU correspond to SEGx on the LCD display (see Figure 5-5). The CPU writes data to and reads data from the display RAM via the I/O buffer, and these read/write operations are independent of the signal read operations for the LCD driver. Accordingly, there are no adverse effects (such as flicker) in the LCD display when display data RAM is accessed asynchronously. Figure 5-5. Display Data RAM
MSB D7 D6 Pixel 1 D5 Pixel 2 D4 D3 Pixel 3 D2 D1 LSB D0
Pixel 4
LCD panel
Pixel 1 Pixel 1
Pixel 2 Pixel 2
Pixel 3 Pixel 3
Pixel 4 Pixel 4
Pixel 1 Pixel 1
Pixel 2 Pixel 2
Pixel 3 Pixel 3
Pixel 4 Pixel 4
X address 00H
X address 01H
D7 D6 D5 D4
0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
SEG1 SEG2 COM0 COM1 COM2 COM3 COM4 LCD display
Display data
5.2.2 X address circuit As shown in Figure 5-6, the display data RAM's X address is specified via the X address register (R3). When using X address increment mode (INC = 0: control register 2 (R1)), the specified X address is incremented (by 1) each time a display data read or write operation is executed. The CPU is able to continuously access the display data. The X address is incremented to 1FH, after which the Y address is incremented after each read or write operation and the X address is set back to 00H. For monochrome (black-and-white) display, the X address is incremented to 0FH, after which the Y address is incremented after each read or write operation and the X address is set back to 00H.
Data Sheet S15730EJ2V0DS
21
PD16498
Figure 5-6. Configuration of X Address Register
D4 D3 D2 D1 D0
0 0 0 0 0 00H
0 0 0 0 1 01H
1 1 1 1 1 1FH
D7 D6 D5 D4 D3 D2 D1 D0
X address
Y address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H
COM output
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38
Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Start
76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH
SEG126 02H 7DH SEG125 03H 7CH SEG127 01H 7EH SEG128 00H 7FH 7FH 00H 7EH 01H 7DH 02H 7CH 03H 7BH 04H 7AH 05H 79H 06H 78H 07H D0
Column address
COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128
SEG7
22
SEG8
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
Data Sheet S15730EJ2V0DS
LCD output D0
1
ADC
0
PD16498
5.2.3 Column address circuit When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in Figure 5-6. Similarly, the static icon address corresponds to the PSEG output. As is shown in Tables 5-1 and 5-2, the correspondence between the display RAM's column address and segment output can be inverted using the ADC flag in control register 1 (R0) (segment driver direction selection flag). This reduces the constraints on chip layout when assembling the LCD module. Table 5-1. Relationship between Column Address and SEG Output
SEG Output ADC (D1) 0 1 SEG1 00H 7FH Column address Column address SEG128 7FH 00H
Table 5-2. Relationship between Column Address for Static Icon and PSEG Output
PSEG Output ADC (D1) 0 1 PSEG1 00H 04H Column address Column address PSEG20 04H 00H
5.2.4 Y address circuit As is shown in Figure 5-4, the Y address register (R4) is used to specify the display data RAM's Y address. When using Y address increment mode (INC = 1: control register 2 (R1)), the specified Y address is incremented (by 1) each time a display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address is incremented to 7FH, after which the X address is incremented after each read or write operation and the Y address is set back to 00H.
5.2.5 Common scan circuit The common scan circuit sets the scan lines for common signals. The scan direction is set using the COMR flag in control register 1 (R0), as shown in Table 5-3. For example, when using 1/80 duty, when COMR = 0 the scan direction is COM1 COM80 and when COMR = 1, the scan direction is COM80 COM1 using the COM80 to COM1 pins. Table 5-3. Relationship between Common Scan Circuit and Scan Direction
COMR (D0) 0 1 COM1 COM128 COM128 COM1
5.2.6 Display start line set As is shown in Figure 5-6, display start line set specifies the Y address that corresponds to the COM1 output for displaying the contents of display data RAM. The display start line setting register (R12) is used to specify the top line in the display. The screen can be scrolled, overwritten, etc. A 7-bit display start address is set to the display start line setting register.
5.2.7 Display data latch circuit The display data latch circuit is used for temporary storage of data that is output to the LCD driver from the display data RAM. The display scan command that sets normal or reverse display mode and the display ON/OFF command control latched data so that there is no effect on the data in the display data RAM.
Data Sheet S15730EJ2V0DS
23
PD16498
5.3 Blink/Reverse Display Circuit
The PD16498 enables blinking display and reverse display in designated parts of the full dot display. A blinking display is achieved by cycling ON/OFF (level 0 when four-level gray scale mode has been selected) at approximately 1 Hz and reverse display is achieved by inverting the display level value. The area designated for blinking is specified via the blink start/end line address registers (R14 and R15), the blink X address register (R13), and the blink data memory access register (R16). First, the blinking display's start and end line addresses are selected via the blink start/end line address registers. Next, the blink X address register (R13) and the blink data memory (R16) are used to select the column for the blinking display. The inversion start/end line address registers (R18 and R19), the inverted X address register (R17), and the inverted data memory access register (R20) are used to select the reverse display area. First, the inversion start/end line address registers (R18 and R19) are set to select the line addresses where the reverse display will start and end. Next, the inverted X address register (R17) and the inverted data memory access register (R20) are used to select the column for the reverse display. The specified blink/inverted X address is incremented (by 1) with each input of blink/reverse display data. The blink RAM and inversion RAM, which have a 128 bit (16 x 8 bit) configuration, are used to store data for blinking display and reverse display respectively. To access the desired bit, simply specify the corresponding X address. The blink/reverse data (data bits D0 to D7 sent from the CPU) correspond to SEGx on the LCD display, as shown in Figure 5-7. After the area and data settings are complete, the BLD bit and IVD bit in the control register 1 (R0) are set to H, at which point the blinking and/or reverse display of data begins. Figure 5-8 illustrates the relationship between the start line address, end line address, blink/reverse data, and LCD display. Table 5-4. Inversion Manipulation and Display
Original Level After Inversion
Four-level gray scale display mode 0, 0 0, 1 1, 0 1, 1 B/W display mode 1 0 0 1 1, 1 1, 0 0, 1 0, 0
Figure 5-7. Correspondence between Blink/Reverse Data and Segments
D3
X address
0 0 0 0 00H
0 0 0 1 01H
1 1 1 1 0FH D7 D6 D5 D4 D3 D2 D1 D0
D2 D1 D0
Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SEG128 00H 7FH
SEG16 70H 0FH
SEG121 07H 78H
SEG122 08H 79H
SEG123 05H 7AH
SEG124 04H 7BH
SEG125 03H 7CH
SEG126 02H 7DH
SEG127 01H 7EH
7FH 00H
7EH 01H
7DH 02H
7CH 03H
7BH 04H
7AH 05H
79H 06H
78H 07H
77H 08H
SEG10 76H 09H
SEG11 75H 0AH
SEG12 74H 0BH
SEG13 73H 0CH
SEG14 72H 0DH
SEG15 71H 0EH
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
24
SEG9
Data Sheet S15730EJ2V0DS
LCD output
Column address
D0 D0
1
ADC
0
PD16498
Figure 5-8. Setting Image of Blink/Reverse Display Area
Blink/revese data
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
001 100 10 00 10 01 10 00 01 01 00 00 10 01 10 0 001 01 00 0 011 00 10 0 011 0010 0 001 0100
Start line
End line
Blinking or reverse display pixels.
Example of sequence for setting blink/reverse display
Start
Blink/inversion start line address register
Blink/inversion end line address register
Blink/inverted X address register
Blink/inverted data memory access register
Data
Write completed ?
Yes
No
Control register 1 (BLD, IVD = H)
End
Data Sheet S15730EJ2V0DS
25
PD16498
5.4
clocks. The clocks from this oscillator are controlled via the CLS pin and the DTY flag in the control register 2 (R1). The clock configuration for the display can be set to suit the target system. The functions of this circuit are described below. *The oscillator for normal and partial display is enabled only when resistors RN and RP have been connected. The DTY flag in the control register 2 (R1) and the CLS pin status are used to switch between the oscillation clocks for normal display and partial display modes. *The divider divides the external clock that has been input for the normal oscillator and the normal display into a clock for partial display. The external clock that is input for the partial oscillator and partial display is also divided for the partial display. *The division level is automatically set for the divider based on the relationship between the ON/OFF status of the divider setting pin (CLS pin) and the duty of the specified partial display, as shown in Table 5-5. Figure 5-9. Oscillator Block
Oscillator
The PD16498 include a CR-type oscillator (R external) for normal and partial display, which generates the display
Selected via DTY/CLS OSCIN1
OSCIN2
Normal display/ partial display oscillator
Signal to select division level for partial display
OSCOUT TOSCSYNC
MUX Partial display divider
To graphic driver
Normal/partial signal CLS Signal to select division level for static icon display Static icon display divider To static icon driver
The relationship between the frame frequency (fFRAME), oscillation frequency (fOSCIN1), and setting duty (in normal display mode) is described below. fFRAME = fOSCIN1 / 8 / N (in four-level gray scale display mode) fFRAME = fOSCIN1 / 4 / N (in B/W display mode) N = 1/N duty (setting duty)
26
Data Sheet S15730EJ2V0DS
PD16498
Table 5-5. Setting of Division Level for Partial Display and Static Icon Display (1/2) In four-level gray scale display mode (GRAY = L, control register 2 (R1))
Display Mode Normal Display Duty Ratio Partial Display Duty Ratio 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/1 to 1/80 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/81 to 1/96 1/25 1/12 H (Partial) 1/38 1/25 Four-level gray scale GRAY = L 1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 H (Partial) 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 H (Partial) 1/38 1/25 1/12 OSCIN1 H(ON) 1/2 1/4 1/8 1/20 OSCIN2 L(OFF) L(OFF) OSCIN1 H(ON) 1/1 1/1 1/2 1/4
Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25
Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12
Division Source OSCIN1 /OSCIN2
Partial Static Icon Divider Normal/Partial Division Division ON/OFF Select DTY Ratio Ratio CLS
Comments
L(OFF) OSCIN1 H(ON) 1/1 OSCIN2 L(OFF) 1/1 1/2 H (Partial) 1/2 OSCIN1 H(ON) 1/2 1/4 L(OFF) OSCIN1 H(ON) 1/1 OSCIN2 L(OFF) 1/1 1/2 1/2 OSCIN1 H(ON) 1/4 1/8 L(OFF) OSCIN1 H(ON) 1/1 OSCIN2 L(OFF) 1/1 1/2 1/2 OSCIN1 H(ON) 1/4 1/8 1/16 1/4
Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /25 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /12 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /12(division ratio) /32 Static icon frame frequency: fOSCIN1 /12(division ratio) /32 Static icon frame frequency: fOSCIN1 /12(division ratio) /32
L (Normal)
-
1/12
Static icon frame frequency: fOSCIN1 /12(division ratio) /32
1/4
1/12
L (Normal)
-
1/16
Static icon frame frequency: fOSCIN1 /16(division ratio) /32
1/4
1/16
L (Normal)
-
1/16
Static icon frame frequency: fOSCIN1 /16(division ratio) /32
1/97 to 1/112
L (Normal)
-
1/20
Static icon frame frequency: fOSCIN1 /20(division ratio) /32
1/113 to 1/128
Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /20(division ratio) /32 Static icon frame frequency: fOSCIN1 /20(division ratio) /32
Static icon frame frequency: fOSCIN1 /20(division ratio) /32
Data Sheet S15730EJ2V0DS
27
PD16498
Table 5-5. Setting of Division Level for Partial Display and Static Icon Display (2/2) In black/white display mode (GRAY = H, control register 2 (R1))
Display Mode Normal Display Duty Ratio Partial Display Duty Ratio 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/1 to 1/80 1/25 1/12 H (Partial) 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/81 to 1/96 1/25 1/12 H (Partial) 1/38 1/25 B/W
GRAY = H
Division Source OSCIN1 /OSCIN2
Divider Partial Static Icon Normal/Partial ON/OFF Division Division Select DTY CLS Ratio Ratio L(OFF)
Comments
OSCIN1 H(ON)
L (Normal)
-
1/6
Static icon frame frequency: fOSCIN1 /6(division ratio) /32
1/1 OSCIN2 L(OFF) 1/1 1/2 1/2 OSCIN1 H(ON) 1/2 1/4 L(OFF) OSCIN1 H(ON) 1/1 OSCIN2 L(OFF) 1/1 1/2 1/2 OSCIN1 H(ON) 1/4 1/8 L(OFF) OSCIN1 H(ON) 1/1 OSCIN2 L(OFF) H (Partial) 1/1 1/2 1/2 OSCIN1 H(ON) 1/4 1/8 L(OFF) OSCIN1 H(ON) 1/1 OSCIN2 L(OFF) H (Partial) 1/1 1/2 1/2 OSCIN1 H(ON) 1/4 1/8 1/10 1/2 L (Normal)
-
1/2
1/6
Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /12
Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /6(division ratio) /32 Static icon frame frequency: fOSCIN1 /6(division ratio) /32 Static icon frame frequency: fOSCIN1 /6(division ratio) /32
L (Normal)
-
1/8
Static icon frame frequency: fOSCIN1 /8(division ratio) /32
1/2
1/8
1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/97 to 1/112 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/25 1/12 1/38 1/113 to 1/128 1/25 1/12 1/38 1/25 1/12
Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12
Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32
L (Normal)
-
1/8
Static icon frame frequency: fOSCIN1 /8(division ratio) /32
1/2
1/8
Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12
Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32
1/10
Static icon frame frequency: fOSCIN1 /10(division ratio) /32
Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12
Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /10(division ratio) /32 Static icon frame frequency: fOSCIN1 /10(division ratio) /32 Static icon frame frequency: fOSCIN1 /10(division ratio) /32
28
Data Sheet S15730EJ2V0DS
PD16498
Table 5-6 shows the relationship between the CLS pin, resistors RN and RP, and the display clock circuit. Table 5-6. Relationship between CLS Pin/Resistors and Display Clock Circuit.
RN Connection Connected Connected Not connected Not connected Not connected RP Connection Connected Not connected Connected Not connected Not connected CLS L H L L H Clock for Normal Display Internal oscillator Internal oscillator External clock External clock External clock Clock for Partial Display Internal oscillator Divided from oscillator clock Internal oscillator External clock Divided from external clock Use Example (Figure 5-8) (A) (B) (C) (D) (E)
Figure 5-10. Clock Use Examples
(A) (B)
OSCIN1 RN RP OSCOUT H or L
OSCIN1
OSCIN2
RN
OSCIN2
OSCOUT
(C)
(D)
fN OSCIN1
fN OSCIN1 fP OSCIN2 OSCIN2
RP OSCOUT Open OSCOUT
(E)
fN OSCIN1
H or L
OSCIN2
Open
OSCOUT
Data Sheet S15730EJ2V0DS
29
PD16498
5.5 Display Timing Generator
The display clock generates timing signals for the line address circuit and the display data latch circuit. Display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver output pins. Reading of the display data is completely independent of the CPU's accessing of the display data RAM. Consequently, there are no adverse effects (such as flicker) on the LCD panel even when the display data RAM is accessed asynchronously in relation to the LCD contents. The internal common timing is generated from the display clock. As shown in Figure 5-11, a driver waveform based on the frame AC drive method is generated for the LCD driver. Figure 5-11. Driver Waveform Based on Frame AC Drive Method
1 frame
12345678
126127 128
12345678
126127 128
RAM DATA VLCD VLC1 VLC2 SEG1 VLC3 VLC4 VSS
VLCD VLC1 VLC2 COM1 VLC3 VLC4 VSS VLCD VLC1 VLC2 COM2 VLC3 VLC4 VSS
VLCD VLC1 VLC2 COM128 VLC3 VLC4 VSS
30
Data Sheet S15730EJ2V0DS
PD16498
5.6 Power Supply Circuit
The power supply circuit supplies the voltage needed to drive the LCD. It includes a booster, voltage regulator, and voltage follower. In the power supply circuit, the power system control register 1 (R32) is used to control the ON/OFF status of the power supply circuit's booster, voltage regulator (also called V regulator), and voltage follower (V/F). This makes it possible to jointly use an external power supply together with certain functions of the on-chip power supply. Table 5-7 shows the function that controls the 3-bit data in the power system control register 1 (R32) and Table 5-8 shows a reference chart of combinations. Table 5-7. Control Values of Bits in Power System Control 1
Item OP2 OP1 OP0 Booster control bit Voltage regulator (V regulator) control bit Voltage follower (V/F) control bit Status 1 ON ON ON 0 OFF OFF OFF
Table 5-8. Reference Chart of Combinations
External Power Supply Input VDD2 VOUT VOUT, AMPOUT VOUT, VLCD to VLC4 Boost-Related Note System Pins Used Not connected Not connected Not connected
Use Status <1> Use on-chip power supply <2> Use V regulator and V/F only <3> Use V/F only <4> Use external power supply only
OP2 OP1 OP0 1 0 0 0 1 1 0 0 1 1 1 0
Booster V Regulator enable disable disable disable enable enable disable disable
V/F enable enable enable disable
Note The boost-related system pins are indicated as pins C1+, C1- to C9+, C9-, and C1A.
5.6.1 Booster A booster that boosts the LCD driving voltage by 2 to 9 times is incorporated in the power supply circuit. Since the booster uses signals from the on-chip oscillator, either the oscillator must be operating or a display clock must be input from an external source. The booster uses pins C1+, C1- to C9+, C9- for normal boost and pins C1A and VDD2 for boost regulation. The wire impedance should be kept as low as possible. The number of boost levels is set using the FBS2, FBS1, and FBS0 flags in power system control 3 (R34), as shown in Table 5-9. Caution If a capacitor is connected to a boost-related system pin that is not for one of these set boost levels, current consumption may increase. Therefore, do not connect any capacitors beyond the number of set boost levels. This also applies for the C1A pin, used to regulate the boost levels. Figure 5-12 describes the connection method for boost levels and capacitors. The partial booster is settings are made using the BST1 and BST0 flags in the power system control 3 (R34), as shown in Table 5-10.
Data Sheet S15730EJ2V0DS
31
PD16498
Figure 5-12. Connection Method for Boost Levels and Capacitors
C9- C1A C1+ C1- C2+ C2- C3+ C3- C4+ C4- C5+ C5- C6+ C6- C7+ C7- C8+ C8- C9+
9x boost mode
C9- C1A
C1+
C1- C2+
C2- C3+
C3- C4+
C4- C5+
C5- C6+
C6- C7+
C7- C8+
C8- C9+
8x boost mode
open
C9- C1A
C1+
C1- C2+
C2- C3+
C3- C4+
C4- C5+
C5- C6+
C6- C7+
C7- C8+
C8- C9+
open
7x boost mode
open
C9- C1A
C1+
C1- C2+
C2- C3+
C3- C4+
C4- C5+
C5- C6+
C6- C7+
C7- C8+
C8- C9+
6x boost mode
open
C9- C1A
C1+
C1- C2+
C2- C3+
C3- C4+
C4- C5+
C5- C6+
C6- C7+
C7- C8+
C8- C9+
5x boost mode
open
C9- C1A
C1+
C1- C2+
C2- C3+
C3- C4+
C4- C5+
C5- C6+
C6- C7+
C7- C8+
C8- C9+
4x boost mode
Table 5-9. Boost Level Settings for Normal Display's Booster
FBS2 0 0 0 0 1 1 1 1 FBS1 0 0 1 1 0 0 1 1 FBS0 0 1 0 1 0 1 0 1 Boost Level 4x 5x 6x 7x 8x 9x Prohibited Prohibited
Table 5-10. Boost Level Settings for Partial Display's Booster
BST1 0 0 1 1 BST0 0 1 0 1 Boost Level 2x 3x 4x Prohibited
32
Data Sheet S15730EJ2V0DS
open
PD16498
5.6.2 Voltage regulator The boost voltage from VOUT is supplied to the voltage regulator and output as the LCD drive voltage VLCD. Since the PD16498 has a 256-step electronic volume function and an on-chip resistor for VLCD voltage regulation, a small number of components can be used to configure a highly accurate voltage regulator.
(1) When using an on-chip resistor for VLCD voltage regulation The on-chip resistor for VLCD voltage regulation and the electronic volume function can be used to regulate the contrast of the LCD contents by controlling the LCD drive voltage VLCD using commands only. In such cases, no external resistor is needed. If VLCD < VOUT, then the value for VLCD can be determined from the following equation. Example Equation VLCD < VOUT VLCD = (1 + Rb ) VEV Ra VLCD = (1 + Rb ) (1 - ) VREG Ra 384 Remark VEV = (1 - ) VREG 384 Figure 5-13. When Using On-Chip Resistor for VLCD Voltage Regulation
VEV (Constant voltage source + electronic volume)
+
VLCD
Rb
Ra
VREG is the IC's on-chip constant voltage source, for which three types of temperature characteristic curves are available. These temperature characteristic curves can be adjusted via settings in the power system control register 1 (R32) (TSC1, TCS0), as shown in Table 5-11. Table 5-11 shows the VREG voltage when TA = 25C. Table 5-11. VREG Voltage When TA = 25C
Status Internal power supply TCS1 0 0 1 1 TCS0 0 1 0 1 Temperature Curve (%/C) -0.06 -0.08 -0.09 -0.12 VREG (TYP.) (V) 1.04 0.98 0.93 0.85
is the electronic volume register (R35) value. Any of 256 statuses can be set as the fetched status for corresponding to the data set to the 8-bit electronic control register. values based on settings in the electronic volume register (R35: normal display mode) and the partial electronic volume register (R36: partial display mode) are listed in Table 5-12.
Data Sheet S15730EJ2V0DS
33
PD16498
Table 5-12. Values Based on Settings in Electronic Volume Register
Register EV7 PEV7 0 0 0 0 1 1 1 EV6 PEV6 0 0 0 0 1 1 1 EV5 PEV5 0 0 0 0 1 1 1 EV4 PEV4 0 0 0 0 1 1 1 EV3 PEV3 0 0 0 0 : 1 1 1 1 1 1 0 1 1 1 0 1 EV2 PEV2 0 0 0 0 EV1 PEV1 0 0 1 1 EV0 PEV0 0 1 0 1 384 254 253 252 : 2 1 0
Rb/Ra is an on-chip resistance factor used for the VLCD voltage regulator. This factor can be controlled at eight levels based on settings in power control register 2 (R33) (VRR2, VRR1, VRR0: normal display mode and PVR2, PVR1, PVR0: partial display mode). Reference voltage values (1 + Rb/Ra) are determined based on 4-bit data set to VLCD's on-chip resistance factor register, as shown in Table 5-13. Table 5-13. Determination of Reference Voltage Values Based on Settings of On-Chip Resistor for VLCD Voltage Regulation
Register VRR2 PVR2 0 0 0 0 1 1 1 1 VRR1 PVR1 0 0 1 1 0 0 1 1 VRR0 PVR0 0 1 0 1 0 1 0 1 5 8 12 13 16 19 21 24 1+Rb/Ra
34
Data Sheet S15730EJ2V0DS
PD16498
(2) When using an external resistor (instead of using the on-chip resistor for VLCD voltage regulation) Instead of using only the on-chip resistor setting for VLCD voltage regulation (IRS = L), resistors (Ra', Rb' and Rc') can be added between VSS and VR, between AMPOUTP and AMPOUT, and between VR and AMPOUT to set the LCD drive voltage VLCD. In such cases, the electronic volume function can be used to control the LCD drive voltage VLCD and to regulate the contrast of the LCD contents via commands. In addition, the PD16498 enable selection between two display values (for normal display and partial display). The value is set using an external division resistor and is automatically selected by the DTY flag in the control register 2 (R1). The VLCD value can be determined using Example 1 (DTY = 0) and Example 2 (DTY = 1) if it is within the range of VLCD < VOUT. Example 1. DTY = 0, normal display mode VLCD = (1 + Rb ) VEV Ra VLCD = (1 + Rb ) (1 - ) VREG Ra 384 Remark VEV (1 -
) VREG 384
Example 2. DTY = 1, partial display mode VLCD = (1+
Rb x Rc ) VEV Ra(Rb + Rc) VLCD = (1+ Rb x Rc ) (1 - ) VREG 384 Ra(Rb + Rc)
Remark VEV = (1 -
) VREG 384
Figure 5-14. When Using External Resistor
+
VLCD
A VR AMPOUT Rb' B
Normal/partial VLC1 regulation select circuit
AMPOUTP
Rc
Ra'
A
B
Normal display mode (DTY = 0)
A
B
Partial display mode (DTY = 1)
Data Sheet S15730EJ2V0DS
35
PD16498
5.6.3 Use of op amp for level power supply control Although the PD16498 includes a circuit designed for low power consumption (HPM1, HPM0 = 0, 0), display quality problems may occur when a large-load LCD panel is used. In such cases, the display quality and power consumption level can be improved by setting. The HPM1 and HPM0 flags in the power system control register 1(R32) to "0, 1" to "1, 1" to switch to the op amp driver capacity for mode settings shown in Table 5-14. Check the actual display quality before deciding which mode to set. If setting high power mode still does not sufficiently improve the display quality, the LCD drive voltage must be provided from an external power source. Table 5-14. Op Amp Mode Setting
HPM1 0 0 1 1 HPM0 0 1 0 1 Mode Setting Normal mode Low power mode High power mode For power ON mode
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Data Sheet S15730EJ2V0DS
PD16498
5.6.4 Application examples of power supply circuits Figures 5-15 to 5-19 show application examples of power supply circuits. Figure 5-15. IRS = H, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
VDD1 VDD2 VOUT
VRS VR AMPOUTP
Open
C1+ C1 C2+ C2 C3+ C3 C4+ C4 C5+ C5 C6+ C6 C7+ C7 C8+ C8 VSS
AMPOUT
VLCD VLC1 VLC2 VLC3 VLC4
C9+ C9 C1A
Figure 5-16. IRS = L, [OP2, OP1, OP0] = [1, 1, 1]
9x boost mode
VRS VDD1 VDD2 VOUT AMPOUTP
Rc
VR
Rb'
C1+ C1 C2+ C2 C3+ C3 C4+ C4 C5+ C5 C6+ C6 C7+ C7 C8+ C8 VSS
AMPOUT
Ra'
VLCD VLC1 VLC2 VLC3 VLC4
C9+ C9 C1A
Data Sheet S15730EJ2V0DS
37
PD16498
Figure 5-17. IRS = H, [OP2, OP1, OP0] = [0, 1, 1]
VRS VDD1 VDD2 VR VOUT AMPOUTP
C1+ C1 C2+ C2 C3+ C3 C4+ Open C4 C5+ C5 C6+ C6 C7+ C7 C8+ C8 VSS Open
AMPOUT
VLCD VLC1 VLC2 VLC3 VLC4
C9+ C9 C1A Open
Figure 5-18. IRS = L, [OP2, OP1, OP0] = [0, 0, 1]
VRS VDD1 VDD2 VR VOUT
C1+ C1 C2+ C2 C3+ C3 C4+ Open C4 C5+ C5 C6+ C6 C7+ C7 C8+ C8 VSS C9+ C9 C1A Open Open Open
AMPOUTP AMPOUT VLCD VLC1 VLC2 VLC3 VLC4
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Data Sheet S15730EJ2V0DS
PD16498
Figure 5-19. IRS = L, [OP2, OP1, OP0] = [0, 0, 0]
VDD1 VDD2 VOUT
C1+ C1 C2+ C2 C3+ C3 C4+ Open C4 C5+ C5 C6+ C6 C7+ C7 C8+ C8 VSS
VRS VR
Open
AMPOUTP AMPOUT
VLCD VLC1 VLC2 VLC3 VLC4
C9+ C9 C1A Open
Data Sheet S15730EJ2V0DS
39
PD16498
5.7 LCD Display Drivers
PD16498 includes both a full dot driver and a static driver icon driver. The full dot driver has a 33-level gray-scale palette
(eight levels of pulse width modulation plus four-frame rate control), from which four levels of gray scale can be selected and registered as the IC's output gray-scale palette. The icon driver has a gray-scale palette with 32-level pulse width modulation, from which four levels of gray scale can be selected and registered for use as the IC's output gray-scale palette (refer to 6.23 Gary scale registers 1 to 4 (R23 to R26)).
5.7.1 Full-dot pulse width modulation The PD16498's pulse width modulator divides the normal LCD display signal's segment pulse width by eight and outputs in synch with the dot output timing based on the ratio (1/8 to 8/8 pulses) for the gray-scale palette that has been selected via a command. Figure 5-20. Full-Dot Pulse Width Modulation
1 frame
12345678
VLCD VLC1 VLC2 SEG1 VLC3 VLC4 VSS
126 127 128
12345678
126 127 128
VLCD VLC1 VLC2 COM1 VLC3 VLC4 VSS
Enlarged section
1
6/8 4/8 1/8 VLCD
2
8/8
3
VLC1
VLC2
Caution There is no pulse width modulation for common outputs.
40
Data Sheet S15730EJ2V0DS
PD16498
The output pulses are output as odd-numbered lines/even-numbered lines or as even-numbered lines/odd-numbered lines, as shown in Figure 5-21. The pulse rising edge and falling edge combinations for each frame are listed in Table 5-15. Figure 5-21. Example of Pulse Width Modulated Output
1 frame
1
2
3
4
5
6
7
8
9 10 11 12
126 127128 1
2
3
4
5
6
7
8
VLCD VLC1 VLC2 VLC3 VLC4 VSS
1
8/8 4/8
2
8/8 3/8 4/8
3
8/8
Data Sheet S15730EJ2V0DS
41
PD16498
Table 5-15. Example of Pulse Width Modulated Output (1/3)
Gray-scale level 0 4n+1 4n+2 4n+3 4n+4 4n+1 4n+2 4n+3 4n+4 4n+1 4n+2 4n+3 4n+4 3 4n+1 4n+2 4n+3 4n+4 4 4n+1 4n+2 4n+3 4n+4 5 4n+1 4n+2 4n+3 4n+4 6 4n+1 4n+2 4n+3 4n+4 7 4n+1 4n+2 4n+3 4n+4 4n+1 4n+2 4n+3 4n+4 9 4n+1 4n+2 4n+3 4n+4 4n+1 4n+2 4n+3 4n+4 COM 1, 2 Frames SEG Odd Numbered 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 2 1 1 1 2 2 1 1 2 2 2 1 2 2 2 2 3 2 2 2 3 3 2 2 SEG Even Numbered 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 2 1 1 1 2 2 1 1 2 2 2 1 2 2 2 2 3 2 2 2 3 3 2 2 3, 4 Frames SEG Odd Numbered 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 1 2 2 2 2 2 2 2 2 2 3 2 2 3 3 SEG Even Numbered 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 1 2 2 2 2 2 2 2 2 2 3 2 2 3 3 5, 6 Frames SEG Odd Numbered 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 2 1 1 2 2 1 1 2 2 1 2 2 2 2 2 2 3 2 2 3 3 2 2 SEG Even Numbered 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 2 1 1 2 2 1 1 2 2 1 2 2 2 2 2 2 3 2 2 3 3 2 2 7, 8 Frames SEG Odd Numbered 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 2 1 1 1 2 2 1 2 2 2 2 2 2 2 2 2 3 2 2 2 3 3 SEG Even Numbered 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 2 1 1 1 2 2 1 2 2 2 2 2 2 2 2 2 3 2 2 2 3 3
1
2
8
10
Remarks 1. n: Integer from 0 to 31. 2. A: Rising edge of pulse during line A output. 3. A: Rising edge of pulse at start of line A output. 4. A: PWM pulse width (A/8)
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Data Sheet S15730EJ2V0DS
PD16498
Table 5-15. Example of Pulse Width Modulated Output (2/3)
Gray-scale level 11 4n+1 4n+2 4n+3 4n+4 12 4n+1 4n+2 4n+3 4n+4 13 4n+1 4n+2 4n+3 4n+4 14 4n+1 4n+2 4n+3 4n+4 15 4n+1 4n+2 4n+3 4n+4 16 4n+1 4n+2 4n+3 4n+4 17 4n+1 4n+2 4n+3 4n+4 18 4n+1 4n+2 4n+3 4n+4 19 4n+1 4n+2 4n+3 4n+4 4n+1 4n+2 4n+3 4n+4 21 4n+1 4n+2 4n+3 4n+4 COM 1, 2 Frames SEG Odd Numbered 3 3 3 2 3 3 3 3 4 3 3 3 4 4 3 3 4 4 4 3 4 4 4 4 5 4 4 4 5 5 4 4 5 5 5 4 5 5 5 5 6 5 5 5 SEG Even Numbered 3 3 3 2 3 3 3 3 4 3 3 3 4 4 3 3 4 4 4 3 4 4 4 4 5 4 4 4 5 5 4 4 5 5 5 4 5 5 5 5 6 5 5 5 3, 4 Frames SEG Odd Numbered 3 2 3 3 3 3 3 3 3 3 3 4 3 3 4 4 4 3 4 4 4 4 4 4 4 4 4 5 4 4 5 5 5 4 5 5 5 5 5 5 5 5 5 6 SEG Even Numbered 3 2 3 3 3 3 3 3 3 3 3 4 3 3 4 4 4 3 4 4 4 4 4 4 4 4 4 5 4 4 5 5 5 4 5 5 5 5 5 5 5 5 5 6 5, 6 Frames SEG Odd Numbered 3 3 2 3 3 3 3 3 3 4 3 3 4 4 3 3 4 4 3 4 4 4 4 4 4 5 4 4 5 5 4 4 5 5 4 5 5 5 5 5 5 6 5 5 SEG Even Numbered 3 3 2 3 3 3 3 3 3 4 3 3 4 4 3 3 4 4 3 4 4 4 4 4 4 5 4 4 5 5 4 4 5 5 4 5 5 5 5 5 5 6 5 5 7, 8 Frames SEG Odd Numbered 2 3 3 3 3 3 3 3 3 3 4 3 3 3 4 4 3 4 4 4 4 4 4 4 4 4 5 4 4 4 5 5 4 5 5 5 5 5 5 5 5 5 6 5 SEG Even Numbered 2 3 3 3 3 3 3 3 3 3 4 3 3 3 4 4 3 4 4 4 4 4 4 4 4 4 5 4 4 4 5 5 4 5 5 5 5 5 5 5 5 5 6 5
20
Remarks 1. n: Integer from 0 to 31. 2. A: Rising edge of pulse during line A output. 3. A: Rising edge of pulse at start of line A output. 4. A: PWM pulse width (A/8)
Data Sheet S15730EJ2V0DS
43
PD16498
Table 5-15. Example of Pulse Width Modulated Output (3/3)
Gray-scale level 22 4n+1 4n+2 4n+3 4n+4 23 4n+1 4n+2 4n+3 4n+4 24 4n+1 4n+2 4n+3 4n+4 25 4n+1 4n+2 4n+3 4n+4 26 4n+1 4n+2 4n+3 4n+4 27 4n+1 4n+2 4n+3 4n+4 28 4n+1 4n+2 4n+3 4n+4 29 4n+1 4n+2 4n+3 4n+4 30 4n+1 4n+2 4n+3 4n+4 31 4n+1 4n+2 4n+3 4n+4 32 4n+1 4n+2 4n+3 4n+4 COM 1, 2 Frames SEG Odd Numbered 6 6 5 5 6 6 6 5 6 6 6 6 7 6 6 6 7 7 6 6 7 7 7 6 7 7 7 7 8 7 7 7 8 8 7 7 8 8 8 7 8 8 8 8 SEG Even Numbered 6 6 5 5 6 6 6 5 6 6 6 6 7 6 6 6 7 7 6 6 7 7 7 6 7 7 7 7 8 7 7 7 8 8 7 7 8 8 8 7 8 8 8 8 3, 4 Frames SEG Odd Numbered 5 5 6 6 6 5 6 6 6 6 6 6 6 6 6 7 6 6 7 7 7 6 7 7 7 7 7 7 7 7 7 8 7 7 8 8 8 7 8 8 8 8 8 8 SEG Even Numbered 5 5 6 6 6 5 6 6 6 6 6 6 6 6 6 7 6 6 7 7 7 6 7 7 7 7 7 7 7 7 7 8 7 7 8 8 8 7 8 8 8 8 8 8 5, 6 Frames SEG Odd Numbered 6 6 5 5 6 6 5 6 6 6 6 6 6 7 6 6 7 7 6 6 7 7 6 7 7 7 7 7 7 8 7 7 8 8 7 7 8 8 7 8 8 8 8 8 SEG Even Numbered 6 6 5 5 6 6 5 6 6 6 6 6 6 7 6 6 7 7 6 6 7 7 6 7 7 7 7 7 7 8 7 7 8 8 7 7 8 8 7 8 8 8 8 8 7, 8 Frames SEG Odd Numbered 5 5 6 6 5 6 6 6 6 6 6 6 6 6 7 6 6 6 7 7 6 7 7 7 7 7 7 7 7 7 8 7 7 7 8 8 7 8 8 8 8 8 8 8 SEG Even Numbered 5 5 6 6 5 6 6 6 6 6 6 6 6 6 7 6 6 6 7 7 6 7 7 7 7 7 7 7 7 7 8 7 7 7 8 8 7 8 8 8 8 8 8 8
Remarks 1. n: Integer from 0 to 31. 2. A: Rising edge of pulse during line A output. 3. A: Rising edge of pulse at start of line A output. 4. A: PWM pulse width (A/8)
44
Data Sheet S15730EJ2V0DS
PD16498
5.7.2 Full-dot frame rate control When combined with pulse width modulation as described in Table 5-15, the PD16498's frame speed is based on 8frame cycles. The subsampling pattern is output based on the palette stored in the IC. Full-Dot Gray-Scale Palette (Output Pulse Width: x/8 Pulses)
Gray scale level 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Frames 1 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 2 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 3 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 4 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 5 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 6 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 7 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 100% 50% OFF data Comments
Remark The gradation in the Comments column are images of the gray-scale level.
Data Sheet S15730EJ2V0DS
45
PD16498
5.7.3 Line shift driver If the frame rate control is performed with equal pulse widths and the same gray scale is displayed on the LCD's full screen, problems such as flickering may occur on the LCD panel. The PD16498 provides a line shift driver as a countermeasure against such screen image problems. Using 8 frames per cycle, the segment PWM output timing is shifted among the common outputs, as shown in Table 5-16 below. Table 5-16. Line Shift Driver
Turn 1 Turn 2 6 F6 F2 F8 F4 F6 F2 F8 F4 F6 F2 * 7 F7 F3 F1 F5 F7 F3 F1 F5 F7 F3 * 8 F8 F4 F2 F6 F8 F4 F2 F6 F8 F4 * 1 F1 F5 F3 F7 F1 F5 F3 F7 F1 F5 * 2 F2 F6 F4 F8 F2 F6 F4 F8 F2 F6 * 3 F3 F7 F5 F1 F3 F7 F5 F1 F3 F7 * 4 F4 F8 F6 F2 F4 F8 F6 F2 F4 F8 * 5 F5 F1 F7 F3 F5 F1 F7 F3 F5 F1 * 6 F6 F2 F8 F4 F6 F2 F8 F4 F6 F2 * 7 F7 F3 F1 F5 F7 F3 F1 F5 F7 F3 * 8 F8 F4 F2 F6 F8 F4 F2 F6 F8 F4 * 1 F1 F5 F3 F7 F1 F5 F3 F7 F1 F5 * 2 F2 F6 F4 F8 F2 F6 F4 F8 F2 F6 * 3 F3 F7 F5 F1 F3 F7 F5 F1 F3 F7 * 4 F4 F8 F6 F2 F4 F8 F6 F2 F4 F8 *
Frame
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 *
1 F1 F5 F3 F7 F1 F5 F3 F7 F1 F5 *
2 F2 F6 F4 F8 F2 F6 F4 F8 F2 F6 *
3 F3 F7 F5 F1 F3 F7 F5 F1 F3 F7 *
4 F4 F8 F6 F2 F4 F8 F6 F2 F4 F8 *
5 F5 F1 F7 F3 F5 F1 F7 F3 F5 F1 *
Remark Fx: Pulse width modulated output frame (See 5.7.2 Full-dot frame rate control). Figure 5-22. Full Dot Frame Rate Control
First frame
1 2 3 4 5
Second frame
127 128
1 2
COM1 COM2 COM3 COM4 COM5
ON OFF ON OFF ON OFF ON OFF ON OFF
COM127 COM128
ON OFF ON OFF
SEG1 SEG2 SEG3 SEG4 SEG5
8 8 8 8 8
1 1 1 1 1
5 5 5 5 5
3 3 3 3 3
7 7 7 7 7
1 1 1 1 1
5 5 5 5 5
3 3 3 3 3
7 7 7 7 7
2 2 2 2 2
6 6 6 6 6
Remark Numerical values in the segment data correspond to the gray-scale palette's frame numbers.
46
Data Sheet S15730EJ2V0DS
PD16498
Figure 5-23. Line Shift Driver Image
Turn 1, first frame
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG126 SEG127 SEG128
COM1 COM2 COM3 COM4 COM5
F1 F5 F3 F7 F1
COM126 COM127 COM128
F5 F3 F7
Turn 1, second frame
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG126 SEG127 SEG128
COM1 COM2 COM3 COM4 COM5
F2 F6 F4 F8 F2
COM126 COM127 COM128
F6 F4 F8
Data Sheet S15730EJ2V0DS
47
PD16498
5.7.4 Display size settings The PD16498 can be set for any duty value from 1/1 to 1/128. This duty setting can be made via bits DT6 to DT0 in the duty setting register (R5), as shown in Table 5-17. Table 5-17. Duty Settings
DT6 0 0 0 0 1 1 1 DT5 0 0 0 0 1 1 1 DT4 0 0 0 0 1 1 1 DT3 0 0 0 0 : 1 1 1 DT2 0 0 0 0 1 1 1 DT1 0 0 1 1 0 1 1 DT0 0 1 0 1 1 0 1 Duty 1/1 1/2 1/3 1/4 : 1/126 1/127 1/128
5.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position The PD16498 enable any setting to be made for the AC driver's inversion position and the inversion position shift amount for each displayed frame via settings made in the AC driver inversion cycle register (R6) and the AC driver inversion position shift register (R7) for normal display mode or via settings made in the partial AC driver inversion cycle register (R8) and the partial AC driver inversion position shift register (R9) for partial display mode. In normal display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed in Table 5-18, based on the NID6 to NID0 bit settings in the AC driver inversion cycle register (R6). If the screen display size has been changed via settings made in the duty setting register (R5), the NIDn values are automatically overwritten by values from the corresponding DTYn bits. The shift amount for each displayed frame can be set as shown in Table 5-19 via settings made to bits MSD6 to MSD0 in the AC driver inversion position shift register (R7). Table 5-18. Settings of AC Driver Inversion Cycle Register (R6)
NID6 0 0 0 0 1 1 1 NID5 0 0 0 0 1 1 1 NID4 0 0 0 0 1 1 1 NID3 0 0 0 0 : 1 1 1 NID2 0 0 0 0 1 1 1 NID1 0 0 1 1 0 1 1 NID0 0 1 0 1 1 0 1 Inverted Lines 1 2 3 4 : 126 127 128
48
Data Sheet S15730EJ2V0DS
PD16498
Table 5-19. Settings of AC Driver Inversion Position Shift Register
MSD6 0 0 0 0 1 1 1 MSD5 0 0 0 0 1 1 1 MSD4 0 0 0 0 1 1 1 MSD3 0 0 0 0 : 1 1 1 1 1 1 0 1 1 1 0 1 MSD2 0 0 0 0 MSD1 0 0 1 1 MSD0 0 1 0 1 Inversion Position Shift Amount 0 1 2 3 : 125 126 127
In partial display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed in Table 5-20, based on the PID5 to PID0 bit settings in the partial AC driver inversion cycle register (R8). The shift amount for each displayed frame can be set as shown in Table 5-21 via settings made to bits PSD5 to PSD0 in the partial AC driver inversion position shift register (R9). Table 5-20. Settings of Partial AC Driver Inversion Cycle Register (R8)
PID5 0 0 0 0 1 1 1 PID4 0 0 0 0 0 0 0 PID3 0 0 0 0 : 0 0 0 0 1 1 1 0 0 1 0 1 PID2 0 0 0 0 PID1 0 0 1 1 PID0 0 1 0 1 Inverted Lines 1 2 3 4 : 36 37 38
Table 5-21. Setting of Partial AC Driver Inversion Position Shift Register (R9)
PSD5 0 0 0 0 1 1 1 PSD4 0 0 0 0 0 0 0 PSD3 0 0 0 0 0 0 0 PSD2 0 0 0 0 : 0 1 1 1 0 0 1 0 1 PSD1 0 0 1 1 PSD0 0 1 0 1 Inversion Position Shift Amount 0 1 2 3 : 35 36 37
Be sure to maintain the following relationship among the display size, AC inversion cycle, and AC inversion position. Display size (duty) AC inversion cycle AC inversion shift amount Caution Setting a small inversion cycle will cause a reduction in the IC's display drive capacity and an increase in the current consumption. We therefore recommend determining the inversion cycle after making a thorough evaluation of the actual LCD panel.
Data Sheet S15730EJ2V0DS
49
PD16498
5.8 Display Modes
5.8.1 Partial display mode The PD16498 include a function for outputting a display that uses only part of the LCD panel. The duty setting for partial display mode can be selected as 1/12, 1/25, or 1/38. Parts of the LCD panel that are outside of the specified display area are scanned with non-select waveforms. The partial start line address register (R21) is used to select which part of the LCD panel to use for the partial display. The display area starts from the start line address and includes the number of lines (12, 25, or 38 lines) that has been specified via the partial display mode setting (R10). When entering this mode, the booster is set to the boost level number that has been set via the power system control register 3 (partial display boost register) (R34) and the display start line is fixed as 00H. In addition, the bias level is automatically changed to the value that has been set via the partial display mode setting (R10). The relationship between the oscillator's frequency and the frame frequency in partial mode is also automatically changed. Figure 5-24 shows the mutual relationship between the partial line start address and the LCD display. When using the partial display mode, the blinking and reverse display functions can be used in the same way as during full-dot display mode. Caution The LCD driver voltage is lower in partial display mode, because the duty is lower than in normal display mode. There may be restrictions on the usable duty depending on the LCD panel characteristics. We recommend determining the partial duty after making a thorough evaluation of the actual LCD panel. Figure 5-24. Relationship Between Partial Line Start Address and LCD Display (in Partial Display Mode)
00H 01H 02H 03H
...
1DH
1EH
1FH
Display start line (00H)
Partial display start line
12, 25, or 38 lines
Non-display areas
Caution In partial display mode, the display start line setting register (R12) command is ignored. When switching from normal display mode to partial display mode or from partial display mode to normal display mode, if an electric charge remains in the smoothing capacitor that is connected between the LCD drive voltage pins (VLCD, VLC1 to VLC4) and the VSS pin, troubles such as a brief all-black display may occur during the mode switching operation. To avoid such troubles, we recommend using the following power-on sequence.
50
Data Sheet S15730EJ2V0DS
PD16498
(1) Normal display partial display switch sequence
DISP = 0 HPM1 = 1, HPM0 = 0
R0
Display OFF
R32
High power mode settings
Switch display mode
R1
Control register 2: switch DTY flag 700 ms (stabilization time for LCD drive voltage and booster)Note
Wait time
HPM1 = X, HPM0 = X DISP = 1
R32
High power mode settings (to mode used during normal display)
R0
Display ON, internal operations status
Note
This 700 ms wait time indicates the time for the VLCD level to change from 15 V to 6 V and thus varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the actual device.
(2) Partial display Normal display switch sequence
DISP = 0 HPM1 = 1, HPM0 = 1
R0
Display OFF
R32
Power ON mode settings
Switch display mode
R1
Control register 2: switch DTY flag 400 ms (stabilization time for LCD drive voltage and booster)Note
Wait time
HPM1 = X, HPM0 = X DISP = 1
R32
High power mode settings (to mode used during normal display)
R0
Display ON, internal operations status
Note
This 400 ms wait time indicates the time for the VLCD level to change from 6 V to 15 V and thus varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the actual device.
Data Sheet S15730EJ2V0DS
51
PD16498
5.8.2 Monochrome (black/white) display The PD16498 provides both a four-level gray scale display mode and a monochrome display mode. To switch to the monochrome display mode, set GRAY = H. The display RAM for one screen of monochrome display mode contents is configured as 128 bits x 128 bits (16 x 8 bits). When using these IC's in monochrome display mode, two screens of data can be written to the display RAM and the two screens can be switched by setting the DSEL bit in the control register 2 (R1). Screen 1 is displayed on the LCD panel when DSEL = L and screen 2 is displayed when DSEL = H. When writing data, the display RAM uses the same X address (00H to 0FH) and Y address and the BWW bit value in the control register 2 (R1) determines which of the two screens the data will be written to: when BWW = L, data is written to screen 1 and when BWW = H, data is written to screen 2, as shown in Figure 5-25. When accessing a specified bit, specify both the X address and Y address. The display data in D0 to D7 (sent from the CPU) corresponds to the SEGx portions of the LCD display, as shown in Figure 5-26. Figure 5-27 shows the relationship between the display data in monochrome display mode and the page/column addresses. Figure 5-25. Display RAM Image in Monochrome (Black/White) Mode
00H 0FH 00H 0FH
Screen 1 DSEL = L (during display) BWW = L (during write)
Screen 2 DSEL = H (during display) BWW = H (during write)
Figure 5-26. Relationship Between Display Data and LCD Display
Data
7 0 0 0 0 0 0 0 0
6 1 1 1 1 1 1 1 0
5 0 0 1 0 0 0 0 0
4 0 0 0 1 0 0 0 0
3 0 0 0 0 1 0 0 0
2 1 1 1 1 1 1 1 0
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 0
7 1 0 0 1 0 0 1 0
6 1 0 0 1 0 0 1 0
5 1 0 0 1 0 0 1 0
4 1 0 0 1 0 0 1 0
3 0 0 0 0 0 0 0 0
2 0 1 1 1 1 1 0 0
1 1 0 0 0 0 0 1 0
0 1 0 0 0 0 0 1 0 LCD display
Display data
52
Data Sheet S15730EJ2V0DS
PD16498
Figure 5-27. Relation Between the Display Data and X/Y Address (in Monochrome Display Mode)
D4 D3 D2 D1 D0 0 0 0 0
0 0 1 1 1
X address
0 0 0
0 1 00H 01H Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 Y address 0FH D7 D6 D5 D4 D3 D2 D1 D0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H
COM output
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38
Start
76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH
SEG13 73H 0CH SEG14 72H 0DH SEG11 75H 0AH SEG12 74H 0BH
COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128
SEG125 03H 7CH
SEG15 71H 0EH
SEG126 02H 7DH
SEG127 05H 7AH
SEG128 04H 7BH
SEG127 01H 7EH
SEG125 07H 78H
SEG126 06H 79H
SEG16 70H 0FH
SEG10 76H 09H
SEG128 00H 7FH
7FH 00H
7EH 01H
7DH 02H
7CH 03H
7BH 04H
7AH 05H
79H 06H
78H 07H
77H 08H
D1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
LCD output D1
Column address
0
1
ADC
Data Sheet S15730EJ2V0DS
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PD16498
5.8.3 Icon display The PD16498 includes 20 segment pins and two common pins (both output the same signal) for displaying icons, independent of the pins used to display graphics. Icons are static-driven and their contrast can be adjusted at 32 levels using phase modulation. The static icon data RAM that is used to record icon display data contains display data (DIS) and blink data (BRI) in a 20-bit x 2 configuration, as shown in Table 5-22 (where ADC = 0) and Table 5-23 (where ADC = 1). Addresses in the static icon data RAM are specified via the static icon address register (R40) and then data is written to memory. The icon blink function operates only when the display data setting is 1, the blink data setting is 1, and the IBL setting is also 1 (R1). Table 5-22. Static Icon Data RAM (ADC = 0)
Static Icon Output Number (PSEGn) Address 00H 01H 02H 03H 04H DIS D7 1 5 9 13 17 BRI D6 DIS D5 2 6 10 14 18 BRI D4 DIS D3 3 7 11 15 19 BRI D2 DIS D1 4 8 12 16 20 BRI D0
Table 5-23. Static Icon Data RAM (ADC = 1)
Static Icon Output Number (PSEGn) Address 00H 01H 02H 03H 04H DIS D7 20 16 12 8 4 BRI D6 DIS D5 19 15 11 7 3 BRI D4 DIS D3 18 14 10 6 2 BRI D2 DIS D1 17 13 9 5 1 BRI D0
Adjustment of contrast is controlled by phase modulation set via the static icon contrast (R42). The pulse width of the ON signal that is output in static drive mode is divided into 32 levels (1/32 to 32/32 pulse width) and the dot output's timing changes during output according to the phase modulation ratio recorded in bits ICS4 to ICS0 of the static icon contrast (R42), as shown in Table 5-24. Table 5-24. Dot Output Timing Changes
ICS4 0 0 0 0 1 1 1 ICS3 0 0 0 0 1 1 1 ICS2 0 0 0 0 : 1 1 1 ICS1 0 0 1 1 0 1 1 ICS0 0 1 0 1 1 0 1 Phase Modulation Ratio 0/32 1/32 2/32 3/32 : 29/32 30/32 31/32
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Data Sheet S15730EJ2V0DS
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Figure 5-28. Phase Modulation Driver Waveforms
1 frame 31/32 to 0/32
VDD1 PSEG VSS
VDD1 PCOM VSS
Example of phase modulation amount for displaying 10H
1 frame
16/32
VDD1 PSEG VSS
16/32
ON
ON
VDD1 PCOM VSS
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PD16498
5.9 Reset
In the PD16498, a reset is executed when the /RES input is at low level or when a reset command is entered. The IC is reset to its default settings. These default settings are listed in the table below.
Register Control register 1 Control register 2 X address register Y address register Duty setting register AC driver inversion cycle register AC driver inversion position shift register Partial AC driver inversion cycle register Partial AC driver inversion position shift register Partial display mode setting register Display memory access register Note Display start line set register Blink X address register Blink start line address register Blink end line address register Blink data memory access register Note Inverted X address register Inversion start line address register Inversion end line address register Inverted data memory access register Note Partial start line address register Gray scale data register 1 (0, 0) Gray scale data register 2 (0, 1) Gray scale data register 3 (1, 0) Gray scale data register 4 (1, 1) Partial gray scale data register 1 (0, 0) Partial gray scale data register 2 (0, 1) Partial gray scale data register 3 (1, 0) Partial gray scale data register 4 (1, 1) Power system control register 1 Power system control register 2 Power system control register 3 Electronic volume register Partial electronic volume register Boost adjustment register Static icon address register Static icon memory access register Note Static icon contrast register RAM test mode setting register Signature read register Number R0 R1 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R30 R32 R33 R34 R35 R36 R37 R40 R41 R42 R44 R45 Disabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled /RES Enabled (DISP flag only) Enabled (IDIS flag only) Disabled Reset Command Enabled
Enabled: Default value is input, Disabled: Default value is not input Note When using the /RES pin to reset, the contents of memory are not retained. Use the reset command to reset if the memory contents need to be retained. Cautions 1. Using the /RES pin to reset initializes the shift clock counter. 2. Always input the reset command as the first command after power ON.
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6. COMMAND REGISTERS
The PD16498 chip uses a combination of RS, /RD (E), and /WR (R,/W) signals to identify data bus signals. Command interpretation and execution is performed using internal timing that does not depend on any external clock. Therefore, processing is very fast and there is usually no need to check for a busy status. The i80 series CPU interface activates read commands using a low pulse input to the /RD pin and activates write commands using a low pulse input to the /WR pin. The M68 series CPU interface sets read mode using a high level input to the R,/W pin and sets write mode using a low level input to the same pin. It activates both read and write com mands using a high-level pulse input to the E pin. Command descriptions using an i80 series CPU interface are shown as follows. The M68 series CPU interface differs from the i80 series CPU interface in that /RD (E) is at high level during status read and display data read operations, as shown in the following command descriptions and command table. If the serial interface has been selected, data is input sequentially starting from D7.
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PD16498
6.1 Control Register 1 (R0) This command specifies the PD16498's general operation modes.
E /RD 1 R,/W /WR 0
RS 1
D7 RMW
D6 DISP
D5 STBY
D4 BLD
D3 IVD
D2 HALT
D1 ADC
D0 COMR
Flag RMW 1: Read/modify/write mode (Address is incremented only after write access) DISP STBY BLD
Function 0: Address is incremented after both write access and read access.
0: Display OFF (All LCD output pins output the VSS level and oscillator and DC/DC converter are operating) 1: Display ON 0: Normal operation 1: Internal operation and oscillation are stopped. Display is OFF. The blinking dots are specified via the blink start/end line address registers and data is set to blink data RAM. 0: Stop blinking 1: Start blinking
IVD
The number of inverted dots is specified via the inversion start/end line address registers and data is set to inverted data RAM. 0: Stop inversion 1: Start inversion
HALT
0: Start internal operation 1: Stop internal operation (since different display modes are used, when switching between partial and normal display modes, the LCD output pins all output the VSS level and the oscillator is operating, but the DC/DC converter is stopped)
ADC Note COMR
Note
The column address corresponding to the SEG outputs (see Table 6-1) for displaying the contents of the display data RAM. This inverts (reverses) the scan direction for common outputs. (See Table 6-2)
Note The reset command must be executed before changing this flag's setting.
Table 6-1. Relationship between Display RAM Column Address and SEG Outputs
SEG Output ADC (D1) 0 1 SEG1 00H 7FH Column addresses Column addresses SEG128 7FH 00H
Table 6-2. Relationship between Common Scan Circuit and Scan Direction
COM Output COMR (D0) 0 1 COM1 COM128 Scan Direction COM128 COM1
Default settings (initial values set by reset command)
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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PD16498
6.2 Control Register 2 (R1) This command specifies the PD16498's general operation modes.
E /RD 1 R,/W /WR 0
RS 1
D7 FDM
D6 IBL
D5 IDIS
D4 DSEL
D3 BWW
D2 GRAY
D1 DTY
D0 INC
Flag FDM Settings for full screen display mode 0: Normal operation
Function
1: Full screen display (set entire screen to ON) (When using four-level gray scale, gray-scale level 32 is output for full screen display). IBL Static icon blink control, icons with "1" as blink data are blinking. 0: Static icon blink OFF 1: Static icon blink ON IDIS 0: Static icon display OFF (All static LCD output pins output the VSS level and oscillator and DC/DC converter are operating) 1: Static icon display ON DSEL Selects display screen during monochrome display mode. 0: Screen 1 1: Screen 2 BWW Selects data write screen during monochrome display mode. 0: Screen 1 1: Screen 2 GRAY Note DTY Note INC 0: 4-level gray scale display mode 1: Monochrome display mode 0: Normal display mode (1/1 to 1/128 duty) 1: Partial display mode (1/12, 1/25, or 1/38 duty, 1/5 or 1/6 bias) 0: Increments X address at each access 1: Increments Y address at each access
Note The HALT command must be executed before changing this flag's setting.
Table 6-3. Relationship between IC's Functions and Display Modes
Item Duty Booster Bias level Gray scale data (1+Rb/Ra) VLCD regulator resistance factor Electronic volume Uses value from the electronic volume register (R35) Uses value from the partial electronic volume register (R36) Normal Display Mode (DTY = 0) 1/1 to 1/128 duty x4, x5, x6, x7, x8, x9 1/11, 1/12, 1/10, 1/9, 1/8, 1/7 Uses levels set to the gray scale data registers (R23 to R26) Uses values of VRR2 to VRR0 in the power system control register 2 (R33) Partial Display Mode (DTY = 1) 1/12, 1/25, or 1/38 duty x2, x3, x4 1/5, 1/6 Uses levels set to the partial gray scale data registers (R27 to R30) Uses values of PVR2 to PVR0 in the power system control register 2 (R33)
Default settings (initial values set by reset command)
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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PD16498
6.3 Reset Command (R2) When this command is input, the IC's registers (R0 to R44) are reset to their initial values. But the contents of memory are retained. Always input the reset command as the first command after power application.
RS 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
6.4 X Address Register (R3) The X address register specifies the X address in the display RAM accessed by the CPU. This address is automatically incremented each time the display RAM is accessed (INC = 0, RMW = 0).
RS 1 D7 - D6 - D5 - D4 XA4 D3 XA3 D2 XA2 D1 XA1 D0 XA0
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 0 D3 0 D2 0 D1 0 D0 0
6.5 Y Address Register (R4) The Y address register specifies the Y address in the display RAM accessed by the CPU. This address is automatically incremented each time the display RAM is accessed (INC = 1, RMW = 0).
RS 1 D7 - D6 YA6 D5 YA5 D4 YA4 D3 YA3 D2 YA2 D1 YA1 D0 YA0
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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6.6 Duty Setting Register (R5) The display duty can be set to any duty ratio between 1/1 and 1/128, as is shown in Table 6-4. Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
RS 1 D7 - D6 DT6 D5 DT5 D4 DT4 D3 DT3 D2 DT2 D1 DT1 D0 DT0
Table 6-4. Duty Setting Register (R5) Settings
DT6 0 0 0 0 1 1 1 DT5 0 0 0 0 1 1 1 DT4 0 0 0 0 1 1 1 DT3 0 0 0 0 : 1 1 1 1 1 1 0 1 1 1 0 1 DT2 0 0 0 0 DT1 0 0 1 1 DT0 0 1 0 1 Duty 1/1 1/2 1/3 1/4 : 1/126 1/127 1/128
Default settings (initial values set by reset command)
D7 - D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1
6.7 AC Driver Inversion Cycle Register (R6) The AC driver's line position for normal display mode can be set as shown in Table 6-5. When a DTYn value is changed in the duty setting register (R5), the NIDn value is automatically overwritten by the DTYn value.
RS 1 D7 - D6 NID6 D5 NID5 D4 NID4 D3 NID3 D2 NID2 D1 NID1 D0 NID0
Table 6-5. AC Driver Inversion Cycle Register (R6) Settings
NID6 0 0 0 0 1 1 1 NID5 0 0 0 0 1 1 1 NID4 0 0 0 0 1 1 1 NID3 0 0 0 0 : 1 1 1 1 1 1 0 1 1 1 0 1 NID2 0 0 0 0 NID1 0 0 1 1 NID0 0 1 0 1 Inversion Line 1 2 3 4 : 126 127 128
Default settings (initial values set by reset command)
D7 - D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1
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PD16498
6.8 AC Driver Inversion Position Shift Register (R7) This register shifts the inversion position for each frame in normal display mode by the shift amount shown in Table 6-6.
RS 1 D7 - D6 MSD6 D5 MSD5 D4 MSD4 D3 MSD3 D2 MSD2 D1 MSD1 D0 MSD0
Table 6-6. AC Driver Inversion Position Shift Register (R7) Settings
MSD5 0 0 0 0 1 1 1 MSD5 0 0 0 0 1 1 1 MSD4 0 0 0 0 1 1 1 MSD3 0 0 0 0 : 1 1 1 1 1 1 0 1 1 1 0 1 MSD2 0 0 0 0 MSD1 0 0 1 1 MSD0 0 1 0 1 Inversion Position Shift Amount 0 1 2 3 : 125 126 127
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.9 Partial AC Driver Inversion Cycle Register (R8) The AC driver's line position can be set as shown in Table 6-7. When a PDTn value is changed in the partial display mode setting register (R10), the PIDn value is automatically overwritten by the PDTn value.
RS 1
D7 -
D6 -
D5 PID5
D4 PID4
D3 PID3
D2 PID2
D1 PID1
D0 PID0
Table 6-7. Partial AC Driver Inversion Cycle Register (R8) Settings
PID5 0 0 0 0 1 1 1 PID4 0 0 0 0 0 0 0 PID3 0 0 0 0 0 0 0 PID2 0 0 0 0 : 0 1 1 1 0 0 1 0 1 PID1 0 0 1 1 PID0 0 1 0 1 Inversion Line 1 2 3 4 : 36 37 38
Default settings (initial values set by reset command)
D7 - D6 - D5 1 D4 0 D3 0 D2 1 D1 0 D0 1
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PD16498
6.10 Partial AC Driver Inversion Position Shift Register (R9) This register shifts the inversion position for each frame by the shift amount shown in Table 6-8.
RS 1 D7 - D6 - D5 PSD5 D4 PSD4 D3 PSD3 D2 PSD2 D1 PSD1 D0 PSD0
Table 6-8. Partial AC Driver Inversion Position Shift Register (R9) Settings
PSD5 0 0 0 0 1 1 1 PSD4 0 0 0 0 0 0 0 PSD3 0 0 0 0 : 0 0 0 0 1 1 1 0 0 1 0 1 PSD2 0 0 0 0 PSD1 0 0 1 1 PSD0 0 1 0 1 Inversion Position Shift Amount 0 1 2 3 : 35 36 37
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 0 D3 0 D2 0 D1 0 D0 0
6.11 Partial Display Mode Setting Register (R10) This command specifies the operation mode to be used in the PD16498's partial display mode. Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations.
RS 1 D7 - D6 - D5 - D4 - D3 PBIS D2 - D1 PDT1 D0 PDT0
Flag PBIS Sets bias level for partial display mode 0: 1/5 bias 1: 1/6 bias PDT1, PDT0 PDT1 0 0 1 1 PDT0 0 1 0 1
Function
Duty in partial display mode 1/38 duty 1/25 duty 1/12 duty Prohibited
With the setting of 1/12 duty, the level voltage (VLCn) for driving the liquid crystal panel may not reach the set value. Thoroughly evaluate the relationship between the duty and driving voltage with the actual system. Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 0 D2 - D1 0 D0 0
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PD16498
6.12 Display Memory Access Register (R11) The display memory access register is used when accessing the display RAM. When this register is write-accessed, data is written directly to the display RAM. When this register is read-accessed, data from the display RAM is first latched to this register before being sent to the bus during the next read operation. Accordingly, one dummy read access is required after display RAM access has been set. When using reset connand to reset, the contents of memory are retained.
RS 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 - D2 - D1 - D0 -
6.13 Display Start Line Setting Register (R12) Display start line set specifies the top line in the display.
RS 1 D7 - D6 DSL6 D5 DSL5 D4 DSL4 D3 DSL3 D2 DSL2 D1 DSL1 D0 DSL0
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.14 Blink X Address Register (R13) The blink X address register specifies the X address of the blink data RAM accessed by the CPU. This address is automatically incremented each time the blink data RAM is accessed.
RS 1 D7 - D6 - D5 - D4 - D3 BXA3 D2 BXA2 D1 BXA1 D0 BXA0
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 0 D2 0 D1 0 D0 0
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PD16498
6.15 Blink Start Line Address Register (R14) The blink start line address register specifies the start line address of the display RAM accessed when the CPU uses blink display mode. The range of blinking lines is determined based on the contents of this register and the blink end line address register.
RS 1 D7 - D6 BSL6 D5 BSL5 D4 BSL4 D3 BSL3 D2 BSL2 D1 BSL1 D0 BSL0 Setting -
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.16 Blink End Line Address Register (R15) The blink end line address register specifies the end line address of the display RAM accessed when the CPU uses blink display mode. The range of blinking lines is determined based on the contents of this register and the blink start line address register.
RS 1 D7 - D6 BEL6 D5 BEL5 D4 BEL4 D3 BEL3 D2 BEL2 D1 BEL1 D0 BEL0 Setting -
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.17 Blink Data Memory Access Register (R16) The blink data memory access register is used to access the blink data RAM. When this register is write-accessed, data is written directly to the blink data RAM. When using reset connand to reset, the contents of memory are retained.
RS 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Data 0 1 Normal Blink
Status
Default settings (initial values set by reset command, all data)
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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PD16498
6.18 Inverted X Address Register (R17) The inverted X address register specifies the X address in the inverted data RAM accessed by the CPU. This address is incremented each time the inversion RAM is accessed.
RS 1 D7 - D6 - D5 - D4 - D3 IXA3 D2 IXA2 D1 IXA1 D0 IXA0
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 0 D2 0 D1 0 D0 0
6.19 Inversion Start Line Address Register (R18) The inversion start line address register specifies the start line address in the display RAM accessed by the CPU when using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and the inversion end line address register.
RS 1 D7 - D6 ISL6 D5 ISL5 D4 ISL4 D3 ISL3 D2 ISL2 D1 ISL1 D0 ISL0
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.20 Inversion End Line Address Register (R19) The inversion end line address register specifies the end line address in the display RAM accessed by the CPU when using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and the inversion start line address register.
RS 1 D7 - D6 IEL6 D5 IEL5 D4 IEL4 D3 IEL3 D2 IEL2 D1 IEL1 D0 IEL0 Setting -
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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6.21 Inverted Data Memory Access Register (R20) The inverted data memory access register is used when accessing the inverted data RAM. When this register is accessed, the data is written directly to the inverted data RAM. When using reset connand to reset, the contents of memory are retained.
RS 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Setting -
Data 0 1 Normal Inverted
Status
Default settings (initial values set by reset command, all data)
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.22 Partial Start Line Address Register (R21) The partial start line address register specifies the start line address in the display RAM accessed by the CPU when using partial display mode. The partial display area is determined as the number of lines specified in the partial display mode setting register (R10), starting from this start line address.
RS 1 D7 - D6 PSL6 D5 PSL5 D4 PSL4 D3 PSL3 D2 PSL2 D1 PSL1 D0 PSL0 Setting -
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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PD16498
6.23 Gray Scale Data Registers 1 to 4 (R23 to R26) The gray scale data registers specify the gray scale level when using normal four-level gray scale display mode. Use of this register optimizes the gray scale display.
Rx R23 R24 R25 R26 Data 0, 0 0, 1 1, 0 1, 1 RS 1 1 1 1 D7 - - - - D7
Disable Disable Disable Disable
D6 - - - - D6
Disable Disable Disable Disable
D5 GD5 GD5 GD5 GD5 D5 0 0 0 0 0
1
D4 GD4 GD4 GD4 GD4 D4 0 0 0 0 : 1
0
D3 GD3 GD3 GD3 GD3 D3 0 0 0 0 1
0
D2 GD2 GD2 GD2 GD2 D2 0 0 0 0 1
0
D1 GD1 GD1 GD1 GD1 D1 0 0 1 1 1
0
D0 GD0 GD0 GD0 GD0 D0 0 1 0 1 1
0
Setting - - - - Gray scale level Level 0 Level 1 Level 2 Level 3 : Level 31
Level 32
Disable Disable
Disable Disable
Default settings (initial values set by reset command, for all gray scale data registers)
D7 - D6 - D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.24 Partial Gray Scale Data Registers 1 to 4 (R27 to R30) The partial gray scale data registers specify the gray scale level when using partial four-level gray scale display mode. Use of this register optimizes the gray scale display.
Rx R27 R28 R29 R30 Data 0, 0 0, 1 1, 0 1, 1 RS 1 1 1 1 D7 - - - - D6 - - - - D5 PGD5 PGD5 PGD5 PGD5 D4 PGD4 PGD4 PGD4 PGD4 D3 PGD3 PGD3 PGD3 PGD3 D2 PGD2 PGD2 PGD2 PGD2 D1 PGD1 PGD1 PGD1 PGD1 D0 PGD0 PGD0 PGD0 PGD0 Setting - - - -
D7
Disable Disable Disable Disable
D6
Disable Disable Disable Disable
D5 0 0 0 0 0 1
D4 0 0 0 0 : 1 0
D3 0 0 0 0 1 0
D2 0 0 0 0 1 0
D1 0 0 1 1 1 0
D0 0 1 0 1 1 0
Gray scale level Level 0 Level 1 Level 2 Level 3 : Level 31 Level 32
Disable Disable
Disable Disable
Default settings (initial values set by reset command, for all partial gray scale data registers)
D7 - D6 - D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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6.25 Power System Control Register 1 (R32) This command sets the PD16498's power system mode.
E /RD 1 R,/W /WR 0
RS 1
D7 HPM1
D6 HPM0
D5 -
D4 TCS2
D3 TCS1
D2 OP2
D1 OP1
D0 OP0
Flag HPM1, HPM0 TCS1, TCS0 OP2 to OP0
Function These flags set the driver mode as shown in Table 6-9. These flags set the value for selecting the VREG voltage's temperature curve, as shown in Table 6-10. These flags control the booster's ON/OFF status, the voltage regulator (V regulator) and voltage follower (V/F). The functions controlled via these three bits by the power control setting command are listed in Table 6-11.
Table 6-9. Driver Mode Setting
HPM1 0 0 1 1 HPM0 0 1 0 1 Mode Setting Normal mode Low-power mode High-power mode Power activation mode
Table 6-10. Selection VREG Voltage's Temperature Curve Value
TCS1 0 0 1 1 TCS0 0 1 0 1 Temperature gradient (%/C) -0.06 -0.08 -0.09 -0.12 VREG (TYP.) (V) 1.04 0.98 0.93 0.85
Table 6-11. Detailed Description of Functions Controlled by Flags of Power System Control 1
Item OP2 OP1 OP0 Booster control flag V regulator control flag Voltage follower control flag Status 1 ON ON ON 0 OFF OFF OFF
Default settings (initial values set by reset command)
D7 0 D6 0 D5 - D4 0 D3 0 D2 1 D1 1 D0 1
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PD16498
6.26 Power System Control Register 2 (R33) This command is used to control the on-chip register for VLCD voltage regualation.
E /RD 1 R,/W /WR 0
RS 1
D7 -
D6 VRR2
D5 VRR1
D4 VRR0
D3 -
D2 PVR2
D1 PVR1
D0 PVR0
Setting -
Flag VRR2 to VRR0
Function When using normal display mode, power system control 2 (VLCD regulator resistance factor setting command) can be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown in Table 6-12 as reference values for (1 + Rb/Ra).
PVR2 to PVR0
When using partial display mode, power system control 2 (VLCD regulator resistance factor setting command) can be used to change the resistance factor at 8 levels. The three flags in power system control 2 set the values shown in Table 6-12 as reference values for (1 + Rb/Ra).
Table 6-12. Reference Values for VLCD Internal Resistance Factor Regulator Register
Register VRR2 PVR2 0 0 0 0 1 1 1 1 VRR1 PVR1 0 0 1 1 0 0 1 1 VRR0 PVR0 0 1 0 1 0 1 0 1 5 8 12 13 16 19 21 24 1+Rb/Ra
Default settings (initial values set by reset command)
D7 - D6 0 D5 0 D4 0 D3 - D2 0 D1 0 D0 0
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Data Sheet S15730EJ2V0DS
PD16498
6.27 Power System Control Register 3 (R34) This command sets the power system mode, including the bias setting for the PD16498's normal display mode and the number of boost levels for partial display mode.
RS 1 D7 BIS2 D6 BIS1 D5 BIS0 D4 FBS2 D3 FBS1 D2 FBS0 D1 BST1 D0 BST0 Setting -
Flag BIS2 to BIS0Note
Function These three flags select the bias ratio as shown below. BIS2 0 0 0 0 1 1 1 1 BIS1 0 0 1 1 0 0 1 1 BIS0 0 1 0 1 0 1 0 1 Bias ratio 1/12 bias 1/11 bias 1/10 bias 1/9 bias 1/8 bias 1/7 bias Prohibited Prohibited
When partial display mode is set, the bias ratio set by the partial mode setting is automatically selected. FBS2 to FBS0Note The number of boost levels in booster for normal display mode is selected as shown below. FBS2 0 0 0 0 1 1 1 1 BST1, BST0 FBS1 0 0 1 1 0 0 1 1 FBS0 0 1 0 1 0 1 0 1 Boost level x4 x5 x6 x7 x8 x9 Prohibited Prohibited
The number of boost levels in the booster for partial display mode is selected as shown below. BST1 0 0 1 1 BST0 0 1 0 1 Boost level x2 x3 x4 Prohibited
Note Be sure to execute the HALT command before changing these flag settings. Default settings (initial values set by reset command)
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
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PD16498
6.28 Electronic Volume Register (R35) The electronic volume register specifies the electronic volume value for adjusting the contrast when using normal display mode. Any value among 256 steps can be selected.
RS 1 D7 EV7 D6 EV6 D5 EV5 D4 EV4 D3 EV3 D2 EV2 D1 EV1 D0 EV0 Setting -
Default settings (initial values set by reset command)
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.29 Partial Electronic Volume Register (R36) The partial electronic volume register specifies the electronic volume value for adjusting the contrast when using partial display mode. Any value among 256 steps can be selected.
RS 1 D7 PEV7 D6 PEV6 D5 PEV5 D4 PEV4 D3 PEV3 D2 PEV2 D1 PEV1 D0 PEV0 Setting -
Default settings (initial values set by reset command)
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
6.30 Boost Adjustment Register (R37) The voltage (range: 1/8 VDD2 to 7/8 VDD2) set to this register is applied to the boost level set for the booster.
RS 1 D7 - D6 - D5 - D4 - D3 - D2 DDC2 D1 DDC1 D0 DDC0 Setting -
Table 6-13. Boost Adjustment Register (R37) Settings
DDC2 0 0 0 0 1 1 1 1 DDC1 0 0 1 1 0 0 1 1 DDC0 0 1 0 1 0 1 0 1 Boost Adjustment Voltage Regulator Circuit Stopped 1/8 VDD2 2/8 VDD2 3/8 VDD2 4/8 VDD2 5/8 VDD2 6/8 VDD2 7/8 VDD2
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 - D2 0 D1 0 D0 0
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Data Sheet S15730EJ2V0DS
PD16498
6.31 Static Icon Address Register (R40) The static icon address specifies the address in the static icon data RAM accessed by the CPU. This address is automatically incremented each time the static icon data RAM is accessed.
RS 1 D7 - D6 - D5 - D4 - D3 - D2 SIA2 D1 SIA1 D0 SIA0
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 - D2 0 D1 0 D0 0
6.32 Static Icon Memory Access Register (R41) The static icon memory access register is used when accessing the static icon data RAM. When this register is writeaccessed, the data is written directly to the static icon data RAM. When using reset command to reset, the contents of this register are retained.
RS 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 - D2 - D1 - D0 -
6.33 Static Icon Contrast Register (R42) The static icon contrast adjusts the contrast of static icons using phase modulation. The pulse width of the ON signal that is output in static drive mode is divided into 32 levels (1/32 to 32/32 pulse width) and the dot output's timing changes during output according to the phase modulation ratio recorded in bits ICS4 to ICS0 of the static icon contrast (R42), as is shown in Table 6-14.
RS 1 D7 - D6 - D5 - D4 0 D3 ICS3 D2 ICS2 D1 ICS1 D0 ICS0
Table 6-14. Static Icon Contrast Register (R42) Setting
ICS4 0 0 0 0 1 1 1 ICS3 0 0 0 0 1 1 1 ICS2 0 0 0 0 : 1 1 1 0 1 1 1 0 1 ICS1 0 0 1 1 ICS0 0 1 0 1 Phase Modulation Ratio 0/32 1/32 2/32 3/32 : 29/32 30/32 31/32
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 0 D2 0 D1 0 D0 0
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PD16498
6.34 RAM Test Mode Setting Register (R44) The RAM test mode setting register directly writes the data for each type of display mode to the display RAM, as shown in Table 6-15.
RS 1 D7 - D6 - D5 - D4 - D3 RTS3 D2 RTS2 D1 RTS1 D0 RTS0
Table 6-15. RAM Test Mode Setting Register (R44) Setting
RTS3 0 0 1 1 1 1 1 1 1 1 RTS2 0 1 0 0 0 0 1 1 1 1 RTS1 0 0 0 0 1 1 0 0 1 1 RTS0 0 0 0 1 0 1 0 1 0 1 Normal operation Displays list of gray scales all 00/pixel all 11/pixel Checker pattern: 00/11 Checker pattern: 11/00 Checker pattern: 01/10 Checker pattern: 10/01 Vertical striped pattern: 00/11 Horizontal striped pattern: 00/11 Write Data
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 0 D2 0 D1 0 D0 0
6.35 Signature Read Register (R45) This commnad is used to read the IC signature set via the SIGIN1 and SIGIN2 pins. This is a read-only register.
RS 1 D7 - D6 - D5 - D4 - D3 - D2 - D1 SIGIN2 D0 SIGIN1
Default settings (initial values set by reset command)
D7 - D6 - D5 - D4 - D3 - D2 - D1 - D0 -
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Data Sheet S15730EJ2V0DS
PD16498
7. LIST OF PD16498 REGISTERS
Index Register 4321 Data Bits 4 3
CS RS 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 IR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63
Register Name
R/W
7
6
5
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Index Register Control register 1 Control register 2 Reset command X address register Y address register Duty setting register AC driver inversion cycle register AC driver inversion position shift register Partial AC driver inversion cycle register Partial AC driver inversion potision shift register Partial display mode setting register Display memory access register Display start line setting register Blink X address register Blink start line address register Blink end line address register Blink data memory access register Inverted X address register Inversion start line address register Inversion end line address register Inverted data memory access register Partial start line address register Gray scale data register 1 (0, 0) Gray scale data register 2 (0, 1) Gray scale data register 3 (1, 0) Gray scale data register 4 (1, 1) Patial gray scale data register 1 (0, 0) Patial gray scale data register 2 (0, 1) Patial gray scale data register 3 (1, 0) Patial gray scale data register 4 (1, 1) Power system control register 1 Power system control register 2 Power system control register 3 Electronic volume register Partial electronic volume register Boost adjustment register
W IR5 IR4 IR3 IR2 IR1 IR0 R/W RMW DISP STBY BLD IVD HALT ADC COMR R/W FDM IBL IDIS DSEL BWW GRAY DTY INC CRES W R/W XA4 XA3 XA2 XA1 XA0 R/W YA6 YA5 YA4 YA3 YA2 YA1 YA0 R/W DT6 DT5 DT4 DT3 DT2 DT1 DT0 R/W NID6 NID5 NID4 NID3 NID2 NID1 NID0 W MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0 W PID4 PID3 PID2 PID1 PID0 W PSD4 PSD3 PSD2 PSD1 PSD0 R/W PBIS PDT1 PDT0 R/W D7 D6 D5 D4 D3 D2 D1 D0 W DSL6 DSL5 DSL4 DSL3 DSL2 DSL1 DSL0 R/W BXA3 BXA2 BXA1 BXA0 R/W BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0 R/W BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0 R/W D7 D6 D5 D4 D3 D2 D1 D0 R/W IXA3 IXA2 IXA1 IXA0 R/W ISL6 ISL5 ISL4 ISL3 ISL2 ISL1 ISL0 R/W IEL6 IEL5 IEL4 IEL3 IEL2 IEL1 IEL0 R/W D7 D6 D5 D4 D3 D2 D1 D0 W PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 W W W W W W W W W W W W W W HPM1 HPM0 VRR2 BIS2 BIS1 EV7 EV6 PEV7 PEV6 GD5 GD5 GD5 GD5 PGD5 PGD5 PGD5 PGD5 GD4 GD4 GD4 GD4 PGD4 PGD4 PGD4 PGD4 TCS1 VRR0 FBS2 EV4 PEV4 GD3 GD3 GD3 GD3 PGD3 PGD3 PGD3 PGD3 GD2 GD2 GD2 GD2 PGD2 PGD2 PGD2 PGD2 GD1 GD1 GD1 GD1 PGD1 PGD1 PGD1 PGD1 OP1 PVR1 BST1 EV1 PEV1 DDC1 GD0 GD0 GD0 GD0 PGD0 PGD0 PGD0 PGD0 OP0 PVR0 BST0 EV0 PEV0 DDC0
VRR1 BIS0 EV5 PEV5
TSC0 OP2 PVR2 FBS1 FBS0 EV3 EV2 PEV3 PEV2 DDC2
Static icon address register Static icon memory access register Static icon contrast register RAM test mode setting register Signature read register
W R/W W W R
D7
D6
D5
SIA2 SIA1 SIA0 D4 D3 D2 D1 D0 ICS4 ICS3 ICS2 ICS1 ICS0 RTS3 RTS2 RTS1 RTS0 SIG2 SIG1
Remark
: Not to use these registers.
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PD16498
8. POWER SUPPLY SEQUENCE
The PD16498 includes power supply circuitry, such as a booster and a voltage follower. When a reset is performed using the /RES pin, the reset function is restricted so as to prevent operation faults that may occur due to noise effects, etc. When electric charge remains in the smoothing capacitor that is connected between the VSS pin and the voltage pins related to the LCD driver (VLCD, VLC1 to VLC4), troubles such as a brief all-black display screen may occur when the power is switched ON or OFF. The following power-on sequence is recommended as a means to avoid such troubles when switching the power ON or OFF. 8.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON Display ON)
Turn power ON when /RES pin = L Power supply stabilization /RES pin = H Command reset Control register 1 DISP = 0, HALT = 1 IC functions set via command input * Control register 1 (DISP = 0, HALT = 1 status is retained) * Control register 2 * Power control register 1 (HPM1, HPM0 = 1, 1) * Power control registers 2, 3 * Electronic volume register * Partial electronic volume register * Boost adjustment register User-specified settings via command input Function settings for gray scale data, etc. Initialization complete Control register 1 DISP = 0, HALT = 0 LCD display screen settings * Display start line setting register * Write screen data, etc. + wait time Power system control register 1 (Mode except HPM1, HPM0 (1, 1)) Control register 1 DISP = 1, HALT = 0
R2 R0
Wait at least 50 s before command input Register reset Display OFF, internal operations stopped
Specification of power activation mode
R0
Display OFF, internal operations started
After internal operations are started, wait at least 400 ms before turning on the LCD display.Note
Cancels V/F mode for power activation
R0
Display ON, internal operation start mode
Note
This 400 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (Power ON Power OFF)).
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Data Sheet S15730EJ2V0DS
PD16498
8.2 Power OFF Sequence (When Using On-Chip Power Supply)
Operation mode DISP = 0, HALT = 0 HPM1 = 1, HPM0 = 0 Set electronic volume register Set partial electronic volume register
R0 R32
Display OFF, internal operation start mode Sets high power mode [EV7, EV6, EV5, EV4, EV3, EV2, EV1, EV0] = [0, 0, 0, 0, 0, 0, 0, 0] [PEV7, PEV6, PEV5, PEV4, PEV3, PEV2, PEV1, PEV0] = [0, 0, 0, 0, 0, 0, 0, 0] Wait at least 1200 ms before power OFF.Note
R35
R36
Power supply OFF
Note
This 1200 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. NEC recommends determining the wait time after making a thorough evaluation of the actual device (refer to 8.5 VOUT, VLCD Voltage Sequence (power ON power OFF)).
8.3 Power ON Sequence (When Using External Driver Power Supply, Power ON Display ON)
Logic power ON when /RES pin = L Power supply stabilization /RES pin = H Command reset DISP = 0, HALT = 1 Initialization via command input (user-specified) Selection of IC functions, etc. DISP = 0, HALT = 0 External LCD driver power supply ON Stabilization of external LCD driver power supply DISP = 1, HALT = 0
VDD1, VDD2 power ON, VOUT = Hi-Z
R2 R0
Wait at least 50 s before command input Register reset Display OFF, internal operations stopped Power system control register 1 (R32) : [OP2, OP1, OP0] = [0 ,0 ,X]
R0
Display OFF, internal operations started VOUT power supply ON
R0
Display ON, internal operations started
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PD16498
8.4 Power Supply OFF Sequence (When Using External Driver Power Supply)
Operation mode DISP = 0, HALT = 0 External driver power supply OFF DISP = 0, HALT = 1 Logic power supply OFF
R0
Display OFF, internal operation start mode VOUT = Hi-Z
R0
Display OFF, internal operations stopped VDD1, VDD2, power supply OFF
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Data Sheet S15730EJ2V0DS
PD16498
8.5 VOUT, VLCD Voltage Sequence (Power ON Power OFF)
0 VDD
/RES pin = 0 Power ON /RES pin = 1 DISP = 0, HALT = 1 Default settings HPM = 3 HALT = 0
VOUT
400 ms Select HPM = 0 to 2 DISP = 1
Normal display DISP = 0 HPM = 2 DTY = 1 700 ms VLCD = 15V 6V Select HPM = 0 to 2 DISP = 1 Partial display DISP = 0 HPM = 3 DTY = 0 400 ms Select HPM = 0 to 2 DISP = 1 Normal display DISP = 0 HPM = 2 EV = 0 1200 ms Power OFF
Dotted line: VOUT Solid line: VLCD
Conditions: VDD: VDD1 = VDD2 = 3.0 V Boost levels: x6 (in normal display mode), x3 (in partial display mode) Capacitors: VLCn pin to Cn+/- pin = 1 F, AMPOUT pin, AMPOUTP pin, VRS pin = 0.1 F Caution Connect a capacitor of less than 0.1 F to both AMPOUT and AMPOUTP pins.
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PD16498
9. USE OF RAM TEST MODE
The PD16498 has a test mode for writing nine types of screen data to display RAM. When using the test mode, be sure to execute via the sequence shown below. If executing the test mode by some other sequence, troubles may appear in the screen display.
Operation mode Control register 1 DISP = 0, STBY = 1 Set RAM test mode Control register 1 DISP = 0, STBY = 0 Wait time Control register 1 DISP = 1 Settings complete
R0
Display OFF, set to standby
R44
Select RAM write data
R0
Display OFF, cancel standby
After internal operations are started, wait at least 1 sec before turning on the LCD display.Note
R0
Display ON
Note
This 1 sec wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the actual device.
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Data Sheet S15730EJ2V0DS
PD16498
10. USE OF STANDBY/HALT MODE
The PD16498 has a standby mode for reducing current consumption, and a HALT mode for switching display mode. Electrical circuits as a DC/DC converter are stopped in standby/HALT mode. When using the standby/HALT mode, be sure to execute via the sequence shown below. If executing the test mode by some other sequence, troubles may appear in the screen display.
Operation mode Control register 1 DISP = 0, STBY = 0, HALT = 0 Control register 1 DISP = 0, STBY = 1(or HALT = 1) Standby mode Power control register 1 (HPM1, HPM0 = 1, 1) Control register 1 DISP = 0, STBY = 0(or HALT = 0) Wait time Power control register 1 (Set except HPM1, HPM0 =1, 1) Control register 1 DISP = 1, HALT = 0
R0
Display OFF
R0
Display OFF, set to standby (HALT)
R32
Reverse sequence to normal operation
R0
Display OFF, cancel standby (HALT)
After internal operations are started, wait at least 400 ms before turning on the LCD display.Note
R32
Set except HPM1, HPM0 = 1,1 (power activation) mode
Display ON, internal operation start mode
Note
This 400 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommends determining the wait time after making a thorough evaluation of the actual device.
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PD16498
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25C, VSS = 0 V)
Parameter Logic system supply voltage Booster supply voltage Driver supply voltage Driver reference supply input voltage Logic system input voltage Logic system output voltage Logic system input/output voltage Driver system input voltage Driver system output voltage Operating ambient temperature Storage temperature VDD1 VDD2 VOUT VLCD, VLC1 to VLC4 VIN1 VOUT1 VI/O1 VIN2 VOUT2 TA Tstg Symbol Ratings -0.3 to +4.0 -0.3 to +4.0 -0.3 to +20.0 -0.3 to VOUT+0.3 -0.3 to VDD1+0.3 -0.3 to VDD1+0.3 -0.3 to VDD1+0.3 -0.3 to VOUT+0.3 -0.3 to VOUT+0.3 -40 to +85 -55 to +125 Unit V V V V V V V V V C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range
Parameter Logic system supply voltage Booster supply voltage Driver system supply voltage Logic system input voltage Driver system supply voltage Maximum setting for LCD driver voltage VDD1 VDD2Note1 VOUT VIN VLCD, VLC1 to VLC4 Note2 VLCD
Note3 Note2
Symbol
MIN. 1.7 2.4 5.5 0 0
TYP.
MAX. 3.6 3.6 18.0 VDD1 VOUT VOUT - 0.5
Unit V V V V V V
Notes 1. VDD1 must be less than or equal to VDD2 2. This item is the recommended parameter when the LCD has an external driver. 3. This item is the recommended parameter when an on-chip power supply circuit drives the LCD. Cautions 1. When using an external LCD driver, be sure to maintain these relations: VSS < VLC4 < VLC3 < VLC2 < VLC1 < VLCD VOUT. 2. Maintain the relations shown in 8. POWER SUPPLY SEQUENCE when turning the power ON or OFF. 3. When using an external resister (when not using an on-chip resister for VLCD adjustment), maintain supply of a voltage between 1.0 V and the VDD1 voltage to the VR and VRS pins.
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Data Sheet S15730EJ2V0DS
PD16498
Electrical Characteristics 1 (Unless Otherwise Specified, TA = -40 to +85C, VDD1 = 1.7 to 3.6 V, VDD2 = 2.4 to 3.6 V)
Parameter High-level input voltage Low-level input voltage High-level input current Low-level input current High-level output voltage Low-level output voltage High-level leakage current Low-level leakage current Symbol VIH VIL IIH1 IIL1 VOH VOL ILOH ILOL Except for P7 (SI), P6 (SCL) and P5 to P0 Except for P7 (SI), P6 (SCL) and P5 to P0 IOUT = -1 mA except OSCOUT IOUT = 1 mA except OSCOUT P7 (SI), P6 (SCL) and P5 to P0, VIN/OUT = VDD1 P7 (SI), P6 (SCL) and P5 to P0, VIN/OUT = VSS Common output ON resistance RCOM Segment output ON resistance RSEG Driver voltage (boost voltage) VOUT VLCn COMn, VOUT = 15 V, VLCD = 13 V, 1/10 bias, |IO| = 50 A VLCn SEGn, VOUT = 15 V, VLCD = 13 V, 1/10 bias, |IO| = 50 A In x5 boost mode, VDD = 3.0 V, Checker pattern display In x6 boost mode, VDD = 3.0 V, Checker pattern display Reference voltage Oscillation frequency VREG Note2 VDD = 3.0 V, TA = 85C, TSC1,TSC0 = 1,1 (temperature characteristic curves:-0.12%/C) fOSCNote3 VDD1 = 3.0 V, TA = 25C, 1/38 duty, in B/W mode, R = 750 k VDD1 = 3.0 V, TA = 25C, 1/38 duty, in B/W mode, R = 3 M 10.6 kHz 36 kHz 0.715 0.775 0.835 V 16.6 V 13.8 V 4 k 4 k -10 VDD1 - 0.5 0.5 10 Conditions MIN. 0.8 VDD1 0.2 VDD1 1 -1 TYP.Note1 MAX. Unit V V
A A
V V
A A
Notes 1. TYP. values are reference values when TA = 25C (except VREG). 2. The reference voltage values (VREG) when TA = 25C are shown below: MIN. = 0.770 V, TYP.= 0.845 V, MAX. = 0.920 V 3. The oscillation frequency fluctuates depending on the wiring capacitance to the external resistor for oscillation.
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PD16498
Electrical Characteristics 2 (Unless Otherwise Specified, TA = -40 to +85C)
Parameter Current consumption (normal mode) Symbol IDD11 Conditions Frame frequency = 70 Hz, B/W all display OFF data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Frame frequency = 70 Hz, B/W checker pattern display data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Current consumption (high-power mode) IDD12 Frame frequency = 70 Hz, B/W all display OFF data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Frame frequency = 70 Hz, B/W checker pattern display data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Current consumption (low-power mode) IDD13 Frame frequency = 70 Hz, B/W all display OFF data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Frame frequency = 70 Hz, B/W checker pattern display data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Current consumption (partial display mode) IDD21 Frame frequency = 70 Hz, B/W all display OFF data output, 1/38 duty, VDD1 = VDD2 = 3.0 V, in x3 boost mode, VLCD = 7.0 V, normal mode Frame frequency = 70 Hz, B/W checker pattern display data output, 1/38 duty, VDD1 = VDD2 = 3.0 V, VLCD = 7.0 V, in x3 boost mode, normal mode Current consumption (standby mode) Current consumption (display icon) IDD23 Icon frame frequency = 125 Hz, B/W all display OFF data output, VDD1 = 3.0 V 18 35 IDD22 VDD1 = VDD2 = 3.0 V 10 105 160 95 140 210 320 135 220 380 560 300 460 250 390 MIN. TYP.Note 180 MAX. 290 Unit
A
A
A
A
A
A
A
A
A
A
Note TYP. values are reference values when TA = 25C.
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Data Sheet S15730EJ2V0DS
PD16498
Required Timing Conditions (Unless Otherwise Specified, TA = -30 to +85C) (1) i80 CPU interface
RS tAS8 /CS1 (CS2 = H) tCYC8 tCCLW, tCCLR /WR, /RD tCCHR, tCCHW tDS8 D0 to D7 (Write) tACC8 D0 to D7 (Read)
When VDD1 = 1.7 V to 2.0 V
Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/RD) Symbol tAH8 tAS8 tCYC8 /WR /RD /WR /RD D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 5 pF, R = 3 k tCCLR RS RS Conditions MIN. 0 0 1000 160 430 160 160 160 0 0 0 470 170 TYP.Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
tf
tr
tAH8
tDH8
tOH8
Control low-level pulse width (/WR) tCCLW Control high-level pulse width (/WR) tCCHW Control high-level pulse width (/RD) tCCHR Data setup time Data hold time /RD access time Output disable time tDS8 tDH8 tACC8 tOH8
Note TYP. values are reference values when TA = 25C.
Data Sheet S15730EJ2V0DS
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PD16498
When VDD1 = 2.0 to 2.5 V
Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/RD) Symbol tAH8 tAS8 tCYC8 /WR /RD /WR /RD D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 5 pF, R = 3 k tCCLR RS RS Conditions MIN. 0 0 600 120 240 120 120 120 0 0 0 280 170 TYP.Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Control low-level pulse width (/WR) tCCLW Control high-level pulse width (/WR) tCCHW Control high-level pulse width (/RD) tCCHR Data setup time Data hold time /RD access time Output disable time tDS8 tDH8 tACC8 tOH8
Note TYP. values are reference values when TA = 25C.
When VDD1 = 2.5 to 3.6 V
Parameter Address hold time Address setup time System cycle time Control low-level pulse width (/RD) Symbol tAH8 tAS8 tCYC8 /WR /RD /WR /RD D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D5, CL = 5 pF, R = 3 k tCCLR RS RS Conditions MIN. 0 0 250 60 120 60 60 60 0 0 0 140 70 TYP.Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Control low-level pulse width (/WR) tCCLW Control high-level pulse width (/WR) tCCHW Control high-level pulse width (/RD) tCCHR Data setup time Data hold time /RD access time Output disable time tDS8 tDH8 tACC8 tOH8
Note TYP. values are reference values when TA = 25C. Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20% or 80% of VDD1.
86
Data Sheet S15730EJ2V0DS
PD16498
(2) M68 CPU interface
RS R,/W tAS6 /CS1 (CS2 = H) tCYC6 tEWHR, tEWHW E tEWLR, tEWLW tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read) tOH6 tDH6 tf tr tAH6
When VDD1 = 1.7 to 2.0 V
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable high pulse width Enable low pulse width Read Write Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 5 pF, R = 3 k E E E E RS RS Conditions MIN. 0 0 1000 160 0 0 0 430 160 160 160 470 170 TYP.Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C.
Data Sheet S15730EJ2V0DS
87
PD16498
When VDD1 = 2.0 to 2.5 V
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable high pulse width Enable low pulse width Read Write Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 5 pF, R = 3 k E E E E RS RS Conditions MIN. 0 0 600 120 0 0 0 240 120 120 120 280 170 TYP.Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C.
When VDD1 = 2.5 to 3.6 V
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable high pulse width Enable low pulse width Read Write Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 5 pF, R = 3 k E E E E RS RS Conditions MIN. 0 0 250 60 0 0 0 120 60 60 60 140 70 TYP.Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Cautions 1. The rise and fall times of input signals (tr and tf) are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) (tCYC6 - tEWLW - tEWHW) or (tr + tf) (tCYC6 - tEWLR - tEWHR). 2. All timing is rated based on 20% or 80% of VDD1.
88
Data Sheet S15730EJ2V0DS
PD16498
(3) Serial interface
tCSS /CS1 (CS2 = H) tSAS RS tSCYC tSLW tSAH
tCSH
SCL tf tr tSDS SI tSDH tSHW
When VDD1 = 1.7 to 2.5 V
Parameter Serial clock cycle SCL high-level pulse width SCL low-level pulse width Address hold time Address setup time Data setup time Data hold time CS - SCL time Symbol tSCYC tSHW tSLW tSAH tSAS tSDS tSDH tCSS tCSH SCL SCL SCL RS RS SI SI CS CS Conditions MIN. 250 100 100 150 150 100 100 150 150 TYP.Note MAX. Unit ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. When VDD1 = 2.5 to 3.6 V
Parameter Serial clock cycle SCL high-level pulse width SCL low-level pulse width Address hold time Address setup time Data setup time Data hold time CS - SCL time Symbol tSCYC tSHW tSLW tSAH tSAS tSDS tSDH tCSS tCSH SCL SCL SCL RS RS SI SI CS CS Conditions MIN. 150 60 60 90 90 60 60 90 90 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns
Note TYP. values are reference values when TA = 25C. Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20% or 80% of VDD1.
Data Sheet S15730EJ2V0DS
89
PD16498
(4) Common
Parameter Clock input 1 Symbol fN Conditions When using OSCIN1, external clock, and on-chip divider, 1/128 duty, B/W mode When using OSCIN1, external clock, and on-chip divider, 1/128 duty, four-level gray scale mode Clock input 2 fP When using OSCIN2, external clock for partial display mode, but not using on-chip divider, B/W mode When using OSCIN2, external clock for partial display mode, but not using on-chip divider, four-level gray scale mode 21.3 50 kHz 10.6 50 kHz 72 150 kHz MIN. TYP.Note 36 MAX. 150 Unit kHz
Note TYP. values are reference values when frame frequency = 70 Hz. Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20% or 80% of VDD1.
Reset timing
tRW
/RES
tR
Internal status During reset
Reset complete
When VDD1 = 1.7 to 2.5 V
Parameter Reset time Reset low pulse width Symbol tR tRW /RES 50 Conditions MIN. TYP.Note MAX. 50 Unit
s s
Note TYP. values are reference values when TA = 25C. When VDD1 = 2.5 to 3.6 V
Parameter Reset time Reset low pulse width Symbol tR tRW /RES 50 Conditions MIN. TYP.Note MAX. 50 Unit
s s
Note TYP. values are reference values when TA = 25C. Caution All timing is rated based on 20% or 80% of VDD1.
90
Data Sheet S15730EJ2V0DS
PD16498
12. CPU INTERFACE (REFERENCE EXAMPLE)
The PD16498 can be connected to either an i80 series CPU or an M68 series CPU. Also, if a serial interface connection is used, the number of signal lines can be reduced. (1) M68 series CPU
VCC
A0 Decoder VIMA
RS /CS1
VDD1 C86
A1 to A15
CPU
D0 to D7 E R/W /RES
P0 to P7 E R,/W
/RES VSS /RESET
GND
(2) i80 series CPU
VCC
A0 Decoder
RS /CS1
VDD1 C86
A1 to A7 /IORQ
CPU
D0 to D7 /RD /WR /RES
P0 to P7 /RD /WR
/RES VSS /RESET
GND
PD16498
PD16498
PSX
PSX
Data Sheet S15730EJ2V0DS
91
PD16498
(3) When using serial interface
VCC
A0 Decoder
RS /CS1
VDD1 C86 H or L
A1 to A7
CPU Port1 /Port2 /RES GND
Open
P0 to P5 SI(P7) SCL(P6)
/RES VSS /RESET
92
Data Sheet S15730EJ2V0DS
PD16498
PSX
PD16498
[MEMO]
Data Sheet S15730EJ2V0DS
93
PD16498
[MEMO]
94
Data Sheet S15730EJ2V0DS
PD16498
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15730EJ2V0DS
95

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